IC PIC MCU FLASH 16K 28-SSOP

PIC24F16KA102-I/SS

Manufacturer Part NumberPIC24F16KA102-I/SS
DescriptionIC PIC MCU FLASH 16K 28-SSOP
ManufacturerMicrochip Technology
SeriesPIC® XLP™ 24F
PIC24F16KA102-I/SS datasheets
 


Specifications of PIC24F16KA102-I/SS

Program Memory TypeFLASHProgram Memory Size16KB (5.5K x 24)
Package / Case28-SSOPCore ProcessorPIC
Core Size16-BitSpeed32MHz
ConnectivityI²C, IrDA, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o24Eeprom Size512 x 8
Ram Size1.5K x 8Voltage - Supply (vcc/vdd)1.8 V ~ 3.6 V
Data ConvertersA/D 9x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CProcessor SeriesPIC24F
CorePICData Bus Width16 bit
Data Ram Size1.5 KBInterface TypeI2C/IrDA/SPI/UART
Maximum Clock Frequency32 MHzNumber Of Programmable I/os24
Number Of Timers3Operating Supply Voltage1.8 V to 3.6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature- 40 COn-chip Adc9-ch x 10-bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithMA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
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PIC24F16KA102 FAMILY
REGISTER 16-1:
SPI1STAT: SPI1 STATUS AND CONTROL REGISTER
R/W-0
U-0
R/W-0
SPIEN
SPISIDL
bit 15
R-0,HSC
R/C-0, HS
R/W-0, HSC
SRMPT
SPIROV
SRXMPT
bit 7
HS = Hardware Settable bit
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
bit 15
SPIEN: SPI1 Enable bit
1 = Enables module and configures SCK1, SDO1, SDI1 and SS1 as serial port pins
0 = Disables module
bit 14
Unimplemented: Read as ‘0’
bit 13
SPISIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-11
Unimplemented: Read as ‘0’
bit 10-8
SPIBEC<2:0>: SPI1 Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPI transfers pending.
Slave mode:
Number of SPI transfers unread.
bit 7
SRMPT: Shift Register (SPI1SR) Empty bit (valid in Enhanced Buffer mode)
1 = SPI1 Shift register is empty and ready to send or receive
0 = SPI1 Shift register is not empty
bit 6
SPIROV: Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded
The user software has not read the previous data in the SPI1BUF register.
0 = No overflow has occurred
bit 5
SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = Receive FIFO is empty
0 = Receive FIFO is not empty
bit 4-2
SISEL<2:0>: SPI1 Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when SPI1 transmit buffer is full (SPITBF bit is set)
110 = Interrupt when last bit is shifted into SPI1SR; as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPI1SR; now the transmit is complete
100 = Interrupt when one data byte is shifted into the SPI1SR; as a result, the TX FIFO has one open spot
011 = Interrupt when SPI1 receive buffer is full (SPIRBF bit set)
010 = Interrupt when SPI1 receive buffer is 3/4 or more full
001 = Interrupt when data is available in receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty
(SRXMPT bit is set)
DS39927B-page 130
U-0
U-0
R-0, HSC
SPIBEC2
R/W-0
R/W-0
R/W-0
SISEL2
SISEL1
SISEL0
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Preliminary
R-0, HSC
R-0, HSC
SPIBEC1
SPIBEC0
bit 8
R-0, HSC
R-0, HSC
SPITBF
SPIRBF
bit 0
C = Clearable bit
x = Bit is unknown
© 2009 Microchip Technology Inc.