IC PIC MCU FLASH 16K 28-SSOP

PIC24F16KA102-I/SS

Manufacturer Part NumberPIC24F16KA102-I/SS
DescriptionIC PIC MCU FLASH 16K 28-SSOP
ManufacturerMicrochip Technology
SeriesPIC® XLP™ 24F
PIC24F16KA102-I/SS datasheets
 


Specifications of PIC24F16KA102-I/SS

Program Memory TypeFLASHProgram Memory Size16KB (5.5K x 24)
Package / Case28-SSOPCore ProcessorPIC
Core Size16-BitSpeed32MHz
ConnectivityI²C, IrDA, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o24Eeprom Size512 x 8
Ram Size1.5K x 8Voltage - Supply (vcc/vdd)1.8 V ~ 3.6 V
Data ConvertersA/D 9x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CProcessor SeriesPIC24F
CorePICData Bus Width16 bit
Data Ram Size1.5 KBInterface TypeI2C/IrDA/SPI/UART
Maximum Clock Frequency32 MHzNumber Of Programmable I/os24
Number Of Timers3Operating Supply Voltage1.8 V to 3.6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature- 40 COn-chip Adc9-ch x 10-bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithMA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
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Page 61/254

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REGISTER 7-1:
RCON: RESET CONTROL REGISTER
bit 1
BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred (the BOR is also set after a POR)
0 = A Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit
1 = A Power-up Reset has occurred
0 = A Power-up Reset has not occurred
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
Note 1:
cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
2:
SWDTEN bit setting.
TABLE 7-1:
RESET FLAG BIT OPERATION
Flag Bit
TRAPR (RCON<15>)
Trap Conflict Event
IOPUWR (RCON<14>)
Illegal Opcode or Uninitialized W Register Access
CM (RCON<9>)
Configuration Mismatch Reset
EXTR (RCON<7>)
MCLR Reset
SWR (RCON<6>)
RESET Instruction
WDTO (RCON<4>)
WDT Time-out
SLEEP (RCON<3>)
PWRSAV #SLEEP Instruction
IDLE (RCON<2>)
PWRSAV #IDLE Instruction
BOR (RCON<1>)
POR, BOR
POR (RCON<0>)
POR
DPSLP (RCON<10>)
PWRSAV #SLEEP instruction with DSCON <DSEN> set
All Reset flag bits may be set or cleared by the user software.
Note:
7.1
Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen as shown in Table 7-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 8.0 “Oscillator Configuration” for
further details.
© 2009 Microchip Technology Inc.
PIC24F16KA102 FAMILY
(1)
(CONTINUED)
Setting Event
TABLE 7-2:
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Reset Type
Clock Source Determinant
POR
FNOSC Configuration bits
(FNOSC<10:8>)
BOR
MCLR
COSC Control bits
(OSCCON<14:12>)
WDTO
SWR
Preliminary
Clearing Event
POR
POR
POR
POR
POR
PWRSAV Instruction, POR
POR
POR
POR
DS39927B-page 59