PIC24F16KA102-I/SS Microchip Technology, PIC24F16KA102-I/SS Datasheet - Page 46
Manufacturer Part Number
IC PIC MCU FLASH 16K 28-SSOP
PIC® XLP™ 24Fr
Specifications of PIC24F16KA102-I/SS
Program Memory Type
Program Memory Size
16KB (5.5K x 24)
Package / Case
I²C, IrDA, SPI, UART/USART
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
512 x 8
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
-40°C ~ 85°C
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature
- 40 C
9-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
The PIC24F Flash program memory array is organized
into rows of 32 instructions or 96 bytes. RTSP allows
the user to erase blocks of 1 row, 2 rows and 4 rows
(32, 64 and 128 instructions) at a time and to program
one row at a time. It is also possible to program single
The 1-row (96 bytes), 2-row (192 bytes) and 4-row
(384 bytes) erase blocks and single row write block
(96 bytes) are edge-aligned, from the beginning of
When data is written to program memory using TBLWT
instructions, the data is not written directly to memory.
Instead, data written using table writes is stored in holding
latches until the programming sequence is executed.
Any number of TBLWT instructions can be executed
and a write will be successfully performed. However,
32 TBLWT instructions are required to write the full row
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions to
load the buffers. Programming is performed by setting
the control bits in the NVMCON register.
Data can be loaded in any order and the holding
registers can be written to multiple times before
performing a write operation. Subsequent writes,
however, will wipe out any previous writes.
Writing to a location multiple times without
erasing it is not recommended.
All of the table write operations are single-word writes
(two instruction cycles), because only the buffers are
programming each row.
Enhanced In-Circuit Serial
Enhanced ICSP uses an on-board bootloader, known
as the program executive, to manage the programming
process. Using an SPI data frame format, the program
executive can erase, program and verify program
memory. For more information on Enhanced ICSP, see
the device programming specification.
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls the
blocks that need to be erased, which memory type is to
be programmed and when the programming cycle
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 55h and AAh to the
NVMKEY register. Refer to Section 5.5 “Programming
Operations” for further details.
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. During a programming or erase operation, the
processor stalls (waits) until the operation is finished.
Setting the WR bit (NVMCON<15>) starts the
operation and the WR bit is automatically cleared when
the operation is finished.
© 2009 Microchip Technology Inc.