MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 104

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MC68HC908RF2CFA

Manufacturer Part Number
MC68HC908RF2CFA
Description
IC MCU W/UHF TX 2K FLASH 32LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908RF2CFA

Core Processor
HC08
Core Size
8-Bit
Speed
4MHz
Peripherals
LVD, POR, PWM, RF Mod
Number Of I /o
12
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-

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Low-Voltage Inhibit (LVI)
8.3.1 False Trip Protection
8.3.2 Short Stop Recovery Option
Data Sheet
104
NOTE:
In addition to forcing a reset condition, the LVI module has a second circuit
dedicated to low-voltage detection. When V
low-voltage comparator asserts the LOWV flag in the LVI status register (LVISR).
In applications that require detecting low batteries, software can monitor by polling
the LOWV bit.
The V
power supply noise. For the LVI module to reset due to a low-power supply, V
must remain at or below the V
See
The LVI has an enable time of t
and long stop recovery (both 4096 CGMXCLK cycles) gives a delay longer than the
LVI enable time for these startup scenarios. There is no period where the MCU is
not protected from a low-power condition. However, when using the short stop
recovery configuration option, the 32 CGMXCLK delay must be greater than the
LVI turn on time to avoid a period in startup where the LVI is not protecting the
MCU.
The LVI is enabled automatically after reset or stop recovery, if the LVISTOP of the
CONFIG register is set. (See
At Level:
V
V
V
V
DD
DD
DD
DD
Table
> V
< V
< V
< V
DD
Freescale Semiconductor, Inc.
LVR
LVR
LVR
LVR
For More Information On This Product,
pin level is digitally filtered to reduce false dead battery detection due to
8-1.
For Number of CGMXCLK Cycles:
Go to: www.freescale.com
Low-Voltage Inhibit (LVI)
< 32 CGMXCLK cycles
> 40 CGMXCLK cycles
V
Between 32 and 40
CGMXCLK cycles
DD
Table 8-1. LOWV Bit Indication
ANY
Section 3. Configuration Register
LVR
EN
. The system stabilization time for power-on reset
level for a minimum 32–40 CGMXCLK cycles.
DD
falls below V
No reset, continue counting CGMXCLK
LVI is guaranteed to generate
Filter counter remains clear
after 32 CGMXCLK cycles
LVI may generate a reset
MC68HC908RF2 — Rev. 4.0
LVS
Result
a reset
, the output of the
(CONFIG).)
MOTOROLA
DD

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