MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 123

• Manufacturer Part Number: MC68HC908RF2CFA
• Description: IC MCU W/UHF TX 2K FLASH 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

10.5.1.2 SWI Instruction
10.5.2 Reset
10.5.3 Break Interrupts
10.5.4 Status Flag Protection in Break Mode
10.6 Low-Power Modes
MC68HC908RF2 — Rev. 4.0
MOTOROLA
NOTE:
The SWI instruction is a non-maskable instruction that causes an interrupt
regardless of the state of the interrupt mask (I bit) in the condition code register.
A software interrupt pushes PC onto the stack. A software interrupt does not push
PC – 1, as a hardware interrupt does.
All reset sources always have higher priority than interrupts and cannot be
arbitrated.
The break module can stop normal program flow at a software-programmable
break point by asserting its break interrupt output. (See
Support.) The SIM puts the CPU into the break state by forcing it to the SWI vector
location. Refer to the break interrupt subsection of each module to see how each
module is affected by the break state.
The SIM controls whether status flags contained in other modules can be cleared
during break mode. The user can select whether flags are protected from being
cleared by properly initializing the break clear flag enable bit (BCFE) in the break
flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in
break mode. This protection allows registers to be freely read and written during
break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break
mode, a flag remains cleared even when break mode is exited. Status flags with a
2-step clearing mechanism — for example, a read of one register followed by the
read or write of another — are protected, even when the first step is accomplished
prior to entering break mode. Upon leaving break mode, execution of the second
step will clear the flag as normal.
Executing the WAIT or STOP instruction puts the MCU in a low power-
consumption mode for standby situations. The SIM holds the CPU in a non-clocked
state. The operation of each of these modes is described here. Both STOP and
WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts
to occur.
Freescale Semiconductor, Inc.
For More Information On This Product,
System Integration Module (SIM)
Go to: www.freescale.com
System Integration Module (SIM)
Section 13. Development
Low-Power Modes
Data Sheet
123