MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 28

• Manufacturer Part Number: MC68HC908RF2CFA
• Description: IC MCU W/UHF TX 2K FLASH 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Memory
2.4 Random-Access Memory (RAM)
2.5 FLASH 2TS Memory
Data Sheet
28
NOTE:
NOTE:
NOTE:
Addresses $0080–$00FF are RAM locations. The location of the stack RAM is
programmable.
For correct operation, the stack pointer must point only to RAM locations.
Before processing an interrupt, the CPU uses five bytes of the stack to save the
contents of the CPU registers.
For M68HC05, M6805, and M146805 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return
address. The stack pointer decrements during pushes and increments during pulls.
Be careful when using nested subroutines. The CPU could overwrite data in the
RAM during a subroutine or during the interrupt stacking operation.
This section describes the operation of the embedded FLASH 2TS memory. This
memory can be read, programmed, and erased from a single external supply. The
program and erase operations are enabled through the use of an internal charge
pump.
The FLASH 2TS memory is appropriately named to describe its 2-transistor
source-select bit cell. The FLASH 2TS memory is an array of 2031 bytes with an
additional 14 bytes of user vectors and one byte for block protection. An erased bit
reads as a 0 and a programmed bit reads as a 1.
The address ranges for the user memory, control register, and vectors are:
This list is the row architecture for the user space array:
•
•
•
•
•
$7800–$7FEE, user space
$7FEF, reserved — optional ICG trim value, see
$FFF0, block protect register
$FE08, FLASH 2TS control register
$FFF2–$FFFF, these locations are reserved for user-defined interrupt and
reset vectors
$7800–$7807 (Row 0)
$7808–$780F (Row 1)
$7810–$7817 (Row 2)
$7818–$781F (Row 3)
$7820–$7827 (Row 4)
------------------------------------
$7FE8–$7FEF (Row 253)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Memory
6.7.3 ICG Trim Register
MC68HC908RF2 — Rev. 4.0
MOTOROLA