MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 133

• Manufacturer Part Number: MC68HC908RF2CFA
• Description: IC MCU W/UHF TX 2K FLASH 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

11.4.1 TIM Counter Prescaler
11.4.2 Input Capture
11.4.3 Output Compare
11.4.4 Unbuffered Output Compare
MC68HC908RF2 — Rev. 4.0
MOTOROLA
NOTE:
NOTE:
The TIM clock source can be one of the seven prescaler outputs or the TIM clock
pin, TCLK. The prescaler generates seven clock rates from the internal bus clock.
The prescaler select bits, PS[2:0], in the TIM status and control register select the
TIM clock source.
With the input capture function, the TIM can capture the time at which an external
event occurs. When an active edge occurs on the pin of an input capture channel,
the TIM latches the contents of the TIM counter into the TIM channel registers,
TCHxH and TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
TIM channel 1 should not be configured in this mode.
With the output compare function, the TIM can generate a periodic pulse with a
programmable polarity, duration, and frequency. When the counter reaches the
value in the registers of an output compare channel, the TIM channel 0 can set,
clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt
requests for both TIM channel 0 and TIM channel 1.
TIM channel 1 does not have an external pin associated with it.
Any output compare channel can generate unbuffered output compare pulses as
described in
changing the output compare value requires writing the new value over the old
value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare
value could cause incorrect operation for up to two counter overflow periods. For
example, writing a new value before the counter reaches the old value but after the
counter reaches the new value prevents any compare during that counter overflow
period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new
value before it is written.
Use these methods to synchronize unbuffered changes in the output compare
value on channel x:
•
When changing to a smaller value, enable channel x output compare
interrupts and write the new value in the output compare interrupt routine.
The output compare interrupt occurs at the end of the current output
compare pulse. The interrupt routine has until the end of the counter
overflow period to write the new value.
Freescale Semiconductor, Inc.
For More Information On This Product,
11.4.3 Output
Go to: www.freescale.com
Timer Interface Module (TIM)
Compare. The pulses are unbuffered because
Timer Interface Module (TIM)
Functional Description
Data Sheet
133