MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 113

• Manufacturer Part Number: MC68HC908RF2CFA
• Description: IC MCU W/UHF TX 2K FLASH 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Data Sheet — MC68HC908RF2
10.1 Introduction
MC68HC908RF2 — Rev. 4.0
MOTOROLA
Note: Writing a 0 clears SBSW
Addr.
$FE00
$FE01
$FE02
SIM Break Flag Control Reg-
SIM Break Status Register
SIM Reset Status Register
Register Name
See page 126.
See page 127.
See page 128.
ister (SBFCR)
(SRSR)
(SBSR)
This section describes the system integration module (SIM). Together with the
central processor unit (CPU), the SIM controls all MCU activities. The SIM is a
system state controller that coordinates CPU and exception timing.
a summary of the SIM input/output (I/O) registers. A block diagram of the SIM is
shown in
The SIM is responsible for:
•
•
•
•
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
POR:
Bus clock generation and control for CPU and peripherals:
–
–
Master reset control, including power-on reset (POR) and computer
operating properly (COP) timeout
Interrupt control:
–
–
–
CPU enable/disable timing
Freescale Semiconductor, Inc.
Figure 10-1. SIM I/O Register Summary
For More Information On This Product,
Figure
Stop/wait/reset/break entry and recovery
Internal clock control
Acknowledge timing
Arbitration control timing
Vector address generation
Bit 7
BCFE
POR
R
1
0
System Integration Module (SIM)
10-2.
Go to: www.freescale.com
= Unimplemented
Section 10. System Integration Module (SIM)
PIN
R
R
6
X
0
COP
5
R
R
X
0
ILOP
4
R
X
R
R
0
= Reserved
ILAD
3
R
X
R
0
2
R
X
R
0
0
See Note
X = Indeterminate
SBSW
Figure 10-1
LVI
1
X
R
0
0
Data Sheet
Bit 0
R
X
R
0
0
113
is