MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 69

• Manufacturer Part Number: MC68HC908RF2CFA
• Description: IC MCU W/UHF TX 2K FLASH 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

6.3.2.4 Digital Loop Filter
MC68HC908RF2 — Rev. 4.0
MOTOROLA
x: Maximum error is independent of value in DDIV[3:0]. DDIV increments or decrements when an addition to DSTG[7:0]
of IBASE Compared
IBASE < 0.85 f
0.85 f
IBASE < 0.95 f
0.95 f
IBASE < 1.05 f
1.05 f
IBASE < 1.15 f
1.15 f
carries or borrows.
Frequency Error
IBASE < f
f
NOM
to f
NOM
NOM
NOM
NOM
< IBASE
NOM
< IBASE
< IBASE
< IBASE
< IBASE
NOM
NOM
NOM
NOM
NOM
The digital loop filter (DLF) uses the outputs of the frequency comparator to adjust
the internal clock (ICLK) clock period. The DLF generates the DCO divider control
bits (DDIV[3:0]) and the DCO stage control bits (DSTG[7:0]), which are fed to the
DCO. The DLF first concatenates the DDIV and DSTG registers
(DDIV[3:0]:DSTG[7:0]) and then adds or subtracts a value dependent on the
relative error in the low-frequency base clock’s period, as shown in
some extreme error conditions, such as operating at a V
specification, the DLF may attempt to use a value above the maximum ($9FF) or
below the minimum ($000). In both cases, the value for DDIV will be between $A
and $F. In this range, the DDIV value will be interpreted the same as $9 (the
slowest condition). Recovering from this condition requires subtracting (increasing
frequency) in the normal fashion until the value is again below $9FF (if the desired
value is $9xx, the value may settle at $Axx through $Fxx, an acceptable operating
condition). If the error is less than ±5 percent, the internal clock generator’s filter
stable indicator (FICGS) is set, indicating relative frequency accuracy to the clock
monitor.
DDVI[3:0]:DSTG[7:0]
Table 6-1. Correction Sizes from DLF to DCO
Freescale Semiconductor, Inc.
For More Information On This Product,
–32 (–$020)
+32 (+$020)
Correction
–8 (–$008)
–1 (–$001)
+1 (+$001)
+8 (+$008)
Internal Clock Generator Module (ICG)
Go to: www.freescale.com
Max
Max
Max
Max
Max
Max
Min
Min
Min
Min
Min
Min
DDIV[3:0]:DSTG[7:0]
Current to New
$xFF to $xDF
$xDF to $xFF
$xFF to $xFE
$xFE to $xFF
$xFF to $xF7
$xF7 to $xFF
$x20 to $x00
$x08 to $x00
$x01 to $x00
$x00 to $x01
$x00 to $x08
$x00 to $x20
Internal Clock Generator Module (ICG)
–0.0625/17.0625
+0.0625/30.9375
–0.0625/31
+0.0625/17
–0.5/17.5
+0.5/30.5
–0.5/31
+0.5/17
DD
–2/31
+2/29
+2/17
–2/19
Relative Correction
level which is out of
Functional Description
in DCO
Table
–0.202%
–0.366%
+0.202%
+0.368%
+1.64%
+2.94%
+6.90%
+11.8%
–6.45%
–10.5%
–1.61%
–2.86%
Data Sheet
6-1. In
69