MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 84

• Manufacturer Part Number: MC68HC908RF2CFA
• Description: IC MCU W/UHF TX 2K FLASH 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Internal Clock Generator Module (ICG)
6.4.8 Trimming Frequency on the Internal Clock Generator
Data Sheet
84
start
store
exit
lda
cmp
lda
add
sta
lda
ldx
mul
rola
rolx
bcc
rorx
inc
stx
lda
cmp
bhi
lda
sta
jmp
jmp
icgcr
#13
#dvfact ;Add the DDIV factor (calculated before
icgdvr
icgdvr
#stfact ;Load the DSTG factor (calculated before coding and
icgdsr
store
icgdsr
icgdvr
#09
exit
#09
icgdvr
error
enable
The unadjusted frequency of the low-frequency base clock (IBASE), when the
comparators in the frequency comparator indicate zero error, will vary as much as
±25 percent due to process, temperature, and voltage dependencies. These
dependencies are in the voltage and current references, the offset of the
comparators, and the internal capacitor. The voltage and temperature
dependencies have been designed to be a maximum of approximately ±1 percent
error. The process dependencies account for the rest.
Fortunately, for an individual part, the process dependencies are constant. An
individual part can operate at approximately ±2 percent variance from its
unadjusted operating point over the entire specification range of the application. If
the unadjusted operating point can be changed, the entire variance can be limited
to ±2 percent.
Figure 6-9. Code Example for Writing DDIV and DSTG
Freescale Semiconductor, Inc.
;DDIV and DSTG modification code example
;Changes DDIV and DSTG according to the initial and
; desired clock period values
;Requires ICGON to be clear (disabled)
;User must previously calculate DVFACT and STFACT by
; the equations listed in the specification
;Modifies X and A registers
;Verify ICGON clear (this will require
; CMIE,CMF,CMON,ICGON,ICGS clear and CS,ECGON,ECGS set)
; coding by the DDIV2 equation)
; multiplied by 128 to make it 0-255 for maximum precision
;Load current stage register contents
;Multiply factor times current value
;Since factor was multiplied by 128,
; result is x6-x0:a7, so put it all in X
;If result is >255, rolx will set carry
; so divide result by two and
; add one to DDIV
;Store value
;Test to see if DDIV too high or low
;Valid range 0-9; too low is FF/FE; too high is 0A/0B
;If DDIV is 0-9, you’re almost done
;Otherwise, maximize period and execute error code
;Jump to code which turns on desired
;clock, clock monitor, interrupts, etc.
For More Information On This Product,
Internal Clock Generator Module (ICG)
Go to: www.freescale.com
MC68HC908RF2 — Rev. 4.0
MOTOROLA