MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 30

• Manufacturer Part Number: MC68HC908RF2CFA
• Description: IC MCU W/UHF TX 2K FLASH 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Memory
2.5.2 FLASH 2TS Charge Pump Frequency Control
Data Sheet
30
NOTE:
BLK0 — Block Erase Control Bit
HVEN — High-Voltage Enable Bit
MARGIN — Margin Read Control Bit
ERASE — Erase Control Bit
PGM — Program Control Bit
The internal charge pump, required for program, margin read, and erase
operations, is designed to operate most efficiently with a 2-MHz clock. The charge
pump clock is derived from the bus clock.
used to select a charge pump frequency based on the bus clock frequency.
Program, margin read, and erase operations cannot be performed if the bus clock
frequency is below 2 MHz.
The charge pump is optimized for 2-MHz operation.
This read/write bit together with BLK1 allows erasing of blocks of varying size.
See
sizes.
This read/write bit enables the charge pump to drive high voltages for program
and erase operations in the array. HVEN can be set only if either PGM = 1 or
ERASE = 1 and the proper sequence for smart programming or erase is
followed.
This read/write bit configures the memory for margin read operation. MARGIN
cannot be set if the HVEN = 1. MARGIN will automatically return to unset (0) if
asserted when HVEN = 1.
This read/write bit configures the memory for erase operation. ERASE is
interlocked with the PGM bit such that both bits cannot be set at the same time.
This read/write bit configures the memory for program operation. PGM is
interlocked with the ERASE bit such that both bits cannot be set at the same
time.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
1 = Margin read operation selected
0 = Margin read operation unselected
1 = Erase operation selected
0 = Erase operation unselected
1 = Program operation selected
0 = Program operation unselected
Freescale Semiconductor, Inc.
2.5.3 FLASH 2TS Erase Operation
For More Information On This Product,
Table 2-2. Charge Pump Clock Frequency
Go to: www.freescale.com
FDIV0
0
1
Memory
Pump Clock Frequency
Bus frequency ÷ 1
Bus frequency ÷ 2
Table 2-2
for a description of available block
shows how the FDIV bits are
MC68HC908RF2 — Rev. 4.0
MOTOROLA