MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 125

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MC68HC908RF2CFA

Manufacturer Part Number
MC68HC908RF2CFA
Description
IC MCU W/UHF TX 2K FLASH 32LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908RF2CFA

Core Processor
HC08
Core Size
8-Bit
Speed
4MHz
Peripherals
LVD, POR, PWM, RF Mod
Number Of I /o
12
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-

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10.6.2 Stop Mode
MC68HC908RF2 — Rev. 4.0
MOTOROLA
NOTE:
In stop mode, the SIM counter is reset and the system clocks are disabled. An
interrupt request from a module can cause an exit from stop mode. Stacking for
interrupts begins after the selected stop recovery time has elapsed. Reset or break
also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK)
in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable
using the SSREC bit in the CONFIG register. If SSREC is set, stop recovery is
reduced from the normal delay of 4096 CGMXCLK cycles down to 32. This is ideal
for applications using canned oscillators that do not require long startup times from
stop mode.
External crystal applications should use the full stop recovery time by clearing the
SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the
SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP instruction until the
beginning of stop recovery. It is then used to time the recovery period.
10-15
CGMXCLK
CPUSTOP
Note: Previous data can be operand data or the STOP opcode, depending on the last instruction.
shows stop mode entry timing.
Freescale Semiconductor, Inc.
RST
IDB
IAB
R/W
For More Information On This Product,
IDB
IAB
$A6
Figure 10-14. Wait Recovery from Internal Reset
System Integration Module (SIM)
Go to: www.freescale.com
STOP ADDR
$6E0B
$A6
Figure 10-15. Stop Mode Entry Timing
PREVIOUS DATA
$A6
STOP ADDR + 1
CYCLES
32
NEXT OPCODE
CYCLES
32
SAME
System Integration Module (SIM)
RST VCT H
SAME
Low-Power Modes
RST VCT L
SAME
Figure
SAME
Data Sheet
125

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