MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 74

• Manufacturer Part Number: MC68HC908RF2CFA
• Description: IC MCU W/UHF TX 2K FLASH 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Internal Clock Generator Module (ICG)
6.3.4.2 Internal Clock Activity Detector
6.3.4.3 External Clock Activity Detector
6.3.5 Clock Selection Circuit
6.3.5.1 Clock Selection Switch
Data Sheet
74
The internal clock activity detector looks for at least one falling edge on the
low-frequency base clock (IBASE) every time the external reference (EREF) is low.
Since EREF is less than half the frequency of IBASE, this should occur every time.
If it does not occur two consecutive times, the internal clock inactivity indicator
(IOFF) is set. IOFF will be cleared the next time there is a falling edge of IBASE
while EREF is low.
The internal clock stable bit (ICGS) is set when IBASE is within approximately 5
percent of the target 307.2 kHz ±25 percent for two consecutive measurements.
ICGS is cleared when IBASE is outside the 5 percent of the target 307.2 kHz ±25
percent, the internal clock generator is disabled (ICGEN is clear), or when IOFF is
set.
The external clock activity detector looks for at least one falling edge on the
external clock (ECLK) every time the internal reference (IREF) is low. Since IREF
is less than half the frequency of ECLK, this should occur every time. If it does not
occur two consecutive times, the external clock inactivity indicator (EOFF) is set.
EOFF will be cleared the next time there is a falling edge of ECLK while IREF is
low.
The external clock stable bit (ECGS) is also generated in the external clock activity
detector. ECGS is set on a falling edge of the external stabilization clock
(ESTBCLK). This will be 4096 ECLK cycles after the external clock generator on
bit (ECGON) is set. ECGS is cleared when the external clock generator is disabled
(ECGON is clear) or when EOFF is set.
The clock selection circuit, shown in
generate the oscillator output clock (CGMXCLK) from either the internal clock
(ICLK) or the external clock (ECLK). The clock selection circuit also contains a
divide-by-two circuit which creates the clock generator output clock (CGMOUT),
which generates the bus clocks.
The clock select switch creates the oscillator output clock (CGMXCLK) from either
the internal clock (ICLK) or the external clock (ECLK), based on the clock select bit
(CS; set selects ECLK, clear selects ICLK). When switching the CS bit, both ICLK
and ECLK must be on (ICGON and ECGON set). The clock being switched to must
also be stable (ICGS or ECGS set).
Freescale Semiconductor, Inc.
For More Information On This Product,
Internal Clock Generator Module (ICG)
Go to: www.freescale.com
Figure
6-5, contains two clock switches which
MC68HC908RF2 — Rev. 4.0
MOTOROLA