MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 25

• Manufacturer Part Number: MC68HC908RF2CFA
• Description: IC MCU W/UHF TX 2K FLASH 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

MC68HC908RF2 — Rev. 4.0
MOTOROLA
Note: Writing a 0 clears SBSW
$003C
$FE00
$0028
$0029
$002A
$002B
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003F
Addr.
↓
↓
Timer Channel 1 Status and
Multiplier Register (ICGMR)
Control Register (ICGDVR)
SIM Break Status Register
Timer Channel 1 Register
Timer Channel 1 Register
Control Register (ICGCR)
ICG DCO Stage Register
Internal Clock Generator
Internal Clock Generator
Internal Clock Generator
Control Register (TSC1)
Register Name
Trim Register (ICGTR)
ICG DCO Divider
Unimplemented
Unimplemented
See page 143.
See page 146.
See page 146.
See page 126.
High (TCH1H)
Low (TCH1L)
See page 88.
See page 90.
See page 90.
See page 91.
See page 91.
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)
(ICGDSR)
Reserved
(SBSR)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
DSTG7
TRIM7
CH1F
Bit 15
CMIE
Bit 7
Bit 7
R
R
R
R
0
0
0
0
1
0
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= Unimplemented
DSTG6
CH1IE
TRIM6
CMF
N6
14
R
R
R
6
0
6
0
0
0
0
Memory
DSTG5
CMON
TRIM5
N5
13
R
R
R
5
0
0
5
0
0
0
0
Indeterminate after reset
Indeterminate after reset
DSTG4
TRIM4
MS1A
Unaffected by reset
CS
N4
12
R
R
R
R
4
0
4
0
1
0
0
= Reserved U = Unaffected X = Indeterminate
DSTG3
ICGON
ELS1B
TRIM3
DDIV3
N3
11
U
R
R
3
0
3
1
0
0
DSTG2
ELS1A
TRIM2
DDIV2
ICGS
N2
10
U
R
R
2
0
2
0
1
0
Input/Output Section
See Note
ECGON
DSTG1
TRIM1
DDIV1
SBSW
TOV1
N1
U
R
1
0
9
1
0
0
0
0
Data Sheet
CH1MAX
Memory
DSTG0
TRIM0
DDIV0
ECGS
Bit 0
Bit 8
Bit 0
N0
U
R
R
0
0
1
0
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