MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 71

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MC68HC908RF2CFA

Manufacturer Part Number
MC68HC908RF2CFA
Description
IC MCU W/UHF TX 2K FLASH 32LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908RF2CFA

Core Processor
HC08
Core Size
8-Bit
Speed
4MHz
Peripherals
LVD, POR, PWM, RF Mod
Number Of I /o
12
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-

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6.3.3.2 External Clock Input Path
6.3.4 Clock Monitor Circuit
MC68HC908RF2 — Rev. 4.0
MOTOROLA
NOTE:
The amplifier is enabled when the ECGON bit is set and stop mode is not enabled.
When the amplifier is enabled, it will be connected between the OSC1 and OSC2
pins. In its typical configuration, the external oscillator requires five external
components:
The external clock input path is the means by which the microcontroller uses an
external clock source. The input to the path is the OSC1 pin and the output is the
external clock (ECLK). The path, which contains input buffering, is enabled when
the ECGON bit is set and stop mode is not enabled.
The ICG contains a clock monitor circuit which, when enabled, will continuously
monitor both the external clock (ECLK) and the internal clock (ICLK) to determine
if either clock source has failed based on these conditions:
Using the clock monitor requires both clocks to be active (ECGON and ICGON are
both set). To enable the clock monitor, both clocks must also be stable (ECGS and
ICGS both set). This is to prevent the use of the clock monitor when a clock is first
turned on and potentially unstable
Although the clock monitor can be enabled only when the both clocks are stable
(ICGS or ECGS is set), the clock monitor will remain enabled if one of the clocks
goes unstable.
The clock monitor only works if the external slow (EXTSLOW) bit in the
configuration register is properly defined with respect to the external frequency
source.
1. Crystal, X
2. Fixed capacitor, C
3. Tuning capacitor, C
4. Feedback resistor, R
5. Series resistor, R
guidelines and may not be required for all ranges of operation, especially
with high frequency crystals). Refer to the crystal manufacturer’s data for
more information.
Either ICLK or ECLK has stopped.
The frequency of IBASE < frequency EREF divided by 4
The frequency of ECLK < frequency of IREF divided by 4
Freescale Semiconductor, Inc.
For More Information On This Product,
Internal Clock Generator Module (ICG)
1
Go to: www.freescale.com
S
1
(included in the diagram to follow strict Pierce oscillator
2
B
(can also be a fixed capacitor)
Internal Clock Generator Module (ICG)
Functional Description
Data Sheet
71

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