MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 82

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MC68HC908RF2CFA

Manufacturer Part Number
MC68HC908RF2CFA
Description
IC MCU W/UHF TX 2K FLASH 32LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908RF2CFA

Core Processor
HC08
Core Size
8-Bit
Speed
4MHz
Peripherals
LVD, POR, PWM, RF Mod
Number Of I /o
12
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-

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Internal Clock Generator Module (ICG)
6.4.6.2 Settling to Within 5 Percent
6.4.6.3 Total Settling Time
Data Sheet
82
Once the clock period is within 15 percent of the desired clock period, the filter
starts making smaller adjustments. When between 15 percent and 5 percent error,
each correction will adjust the clock period between 1.61 percent and 2.94 percent.
In this mode, a maximum of eight corrections will be required to get to less than 5
percent error. Since the clock period is relatively close to desired, each correction
takes approximately the same period of time, or 4*t
clock stable bit (ICGS) will be set and the clock frequency is usable, although the
error will be as high as 5 percent. The total time to this point is:
Once the clock period is within 5 percent of the desired clock period, the filter starts
making minimum adjustments. In this mode, each correction will adjust the
frequency between 0.202 percent and 0.368 percent. A maximum of 24 corrections
will be required to get to the minimum error. Each correction takes approximately
the same period of time or 4*t
percent, this makes 32 corrections (128*t
minimum error. The total time to the minimum error is:
The equations for t
periods t
due to process, temperature, and voltage must be considered. Additionally, other
process factors and noise can affect the actual tolerances of the points at which the
filter changes modes. This means a worst case adjustment of up to 35 percent
(ICLK clock period tolerance plus 10 percent) must be added. This adjustment can
be reduced with trimming.
1/ (307.2 kHz)
1/ (6.45 MHz)
1/ (25.8 MHz)
1/ (25.8 MHz)
Freescale Semiconductor, Inc.
1
t
For More Information On This Product,
1
and t
Internal Clock Generator Module (ICG)
2
, not the nominal. This means the variability in the ICLK frequency
Go to: www.freescale.com
Table 6-4. Typical Settling Time Examples
15
, t
t
tot
t
5
5
1/ (307.2 kHz)
1/ (25.8 MHz)
1/ (6.45 MHz)
1/ (25.8 MHz)
, and t
=
=
Table 6-4
abs 44N t
abs 44N t
t
2
IBASE
tot
[
[
are dependent on the actual initial and final clock
. Added to the corrections for 15 percent to 5
shows some typical values for settling time.
(
(
1
1
84
84
21
N
IBASE
1
t
t
2
2
)
)
]
]
) to get from 15 percent to the
+
+
11.9 ms
430 µs
107 µs
141 µs
32t
128t
t
15
IBASE
IBASE
IBASE
. At this point, the internal
MC68HC908RF2 — Rev. 4.0
12.0 ms
535 µs
212 µs
246 µs
t
5
MOTOROLA
12.3 ms
850 µs
525 µs
560 µs
t
tot

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