MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 29

• Manufacturer Part Number: MC68HC908RF2CFA
• Description: IC MCU W/UHF TX 2K FLASH 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

2.5.1 FLASH 2TS Control Register
MC68HC908RF2 — Rev. 4.0
MOTOROLA
NOTE:
NOTE:
Program and erase operations are facilitated through control bits in a memory
mapped register. Details for these operations appear later in this section. Memory
in the FLASH 2TS array is organized into pages within rows. For the 2-Kbyte array
on the MC68HC908RF2, the page size is one byte. There are eight pages (or eight
bytes) per row. Programming operations are performed on a page basis, one byte
at a time. Erase operations are performed on a block basis. The minimum block
size is one row of eight bytes. Refer to
Sometimes a program disturb condition, in which case an erased bit on the row
being programmed unintentionally becomes programmed, occurs. The embedded
smart programming algorithm implements a margin read technique to avoid
program disturb. The margin read step of the smart programming algorithm is used
to ensure programmed bits are programmed to sufficient margin for data retention
over the device’s lifetime. In the application code, perform an erase operation after
eight program operations (on the same row) to further avoid program disturb.
For availability of programming tools and more information, contact a local
Motorola representative.
A security feature prevents viewing of the FLASH 2TS contents.
The FLASH 2TS control register (FLCR) controls program, erase, and margin read
operations.
FDIV0 — Frequency Divide Control Bit
BLK1 — Block Erase Control Bit
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH 2TS difficult for unauthorized users.
Address:
This read/write bit selects the factor by which the charge pump clock is divided
from the system clock. See
Control.
This read/write bit together with BLK0 allows erasing of blocks of varying size.
See
sizes.
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
2.5.3 FLASH 2TS Erase Operation
For More Information On This Product,
$FE08
Bit 7
Figure 2-3. FLASH 2TS Control Register (FLCR)
0
0
Go to: www.freescale.com
= Unimplemented
FDIV0
6
0
Memory
BLK1
2.5.2 FLASH 2TS Charge Pump Frequency
5
0
Table 2-3
BLK0
4
0
for a description of available block
HVEN
for additional block size options.
3
0
MARGIN
2
0
FLASH 2TS Memory
(1)
ERASE
1
0
Data Sheet
Memory
PGM
Bit 0
0
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