MC68HC908RF2CFA Freescale Semiconductor, MC68HC908RF2CFA Datasheet - Page 79

• Manufacturer Part Number: MC68HC908RF2CFA
• Description: IC MCU W/UHF TX 2K FLASH 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

6.4.4.2 Binary Weighted Divider
6.4.4.3 Variable-Delay Ring Oscillator
6.4.4.4 Ring Oscillator Fine-Adjust Circuit
MC68HC908RF2 — Rev. 4.0
MOTOROLA
The binary weighted divider divides the output of the ring oscillator by a power of 2,
specified by the DCO divider control bits (DDIV[3:0]). DDIV maximizes at %1001
(values of %1010 through %1111 are interpreted as %1001), which corresponds
to a divide by 512. When DDIV is %0000, the ring oscillator’s output is divided by 1.
Incrementing DDIV by 1 will double the period; decrementing DDIV will halve the
period. The DLF cannot directly increment or decrement DDIV; DDIV is only
incremented or decremented when an addition or subtraction to DSTG carries or
borrows.
The variable-delay ring oscillator’s period is adjustable from 17 to 31 stage delays,
in increments of two, based on the upper three DCO stage control bits (DSTG[7:5]).
A DSTG[7:5] of %000 corresponds to 17 stage delays; DSTG[7:5] of %111
corresponds to 31 stage delays. Adjusting the DSTG[5] bit has a 6.45 percent to
11.8 percent effect on the output frequency. This also corresponds to the size
correction made when the frequency error is greater than ±15 percent. The value
of the binary weighted divider does not affect the relative change in output clock
period for a given change in DSTG[7:5].
The ring oscillator fine-adjust circuit causes the ring oscillator to effectively operate
at non-integer numbers of stage delays by operating at two different points for a
variable number of cycles specified by the lower five DCO stage control bits
(DSTG[4:0]). For example, when DSTG[7:5] is %011, the ring oscillator nominally
operates at 23 stage delays. When DSTG[4:0] is %00000, the ring will always
operate at 23 stage delays. When DSTG[4:0] is %00001, the ring will operate at 25
stage delays for one of 32 cycles and at 23 stage delays for 31 of 32 cycles.
%0101–%1001 (max)
Freescale Semiconductor, Inc.
%0000 (min)
%0000 (min)
DDIV[3:0]
For More Information On This Product,
%0001
%0001
%0010
%0010
%0011
%0100
Internal Clock Generator Module (ICG)
Go to: www.freescale.com
Table 6-3. Quantization Error in ICLK
ICLK Cycles
≥ 32
≥ 16
≥ 8
≥ 4
≥ 2
≥ 1
4
4
4
Internal Clock Generator Module (ICG)
Bus Cycles
≥ 8
≥ 4
≥ 2
≥ 1
≥ 1
≥ 1
1
1
1
0.202%–0.368%
0.202%–0.368%
0.403%–0.735%
0.202%–0.368%
0.202%–0.368%
0.202%–0.368%
0.202%–0.368%
0.806%–1.47%
1.61%–2.94%
t
ICLK
Usage Notes
Q-ERR
Data Sheet
79