R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1028

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

20. Graphics Data Translation Accelerator (GDTA)
20.3.17 CL Input Y Padding Size Setting Register (CLIYPR)
CLIYPR is in the CL register block and sets the input Y padding size in byte units.
Notes: 1. Addition is performed taking that 1 pixel = 1 byte.
Rev.1.00 Jan. 10, 2008 Page 996 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 12 ⎯
11 to 0
R/W:
R/W:
BIt:
BIt:
2. CLWR (bytes) + CLIYPR (bytes) should be 32 bytes × n (n: an integer greater than 0)
Bit Name
CL_IYP
31
15
⎯
⎯
⎯
⎯
0
0
30
⎯
⎯
14
⎯
⎯
0
0
29
⎯
⎯
13
⎯
⎯
0
0
Initial
Value
All 0
All 0
28
12
⎯
⎯
⎯
⎯
0
0
R/W
R/W
⎯
R/W
27
11
⎯
⎯
0
0
R/W
26
10
⎯
⎯
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Input Y padding size setting
Should be set in byte units.
Value set should be 2 × n (n: an integer greater than 0)
R/W
25
⎯
⎯
0
9
0
R/W
24
⎯
⎯
0
8
0
R/W
23
⎯
⎯
0
7
0
R/W
22
⎯
⎯
0
6
0
CL_IYP
R/W
21
⎯
⎯
0
5
0
R/W
20
⎯
⎯
0
4
0
R/W
19
⎯
⎯
0
3
0
R/W
18
⎯
⎯
0
2
0
R/W
17
⎯
⎯
0
1
0
R/W
16
⎯
⎯
0
0
0