R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 956

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 924 of 1658
REJ09B0261-0100
Bit
30 to 28 DEA
27
Bit Name
⎯
Initial
Value
0
0
R/W
R/W
R
Internal
Update
None
⎯
Description
DE Output Timing Adjustment
000: Adjustment of output timing is not
001: The DE signal is output at the rising edge,
010: The DE signal is output at the rising edge,
011: The DE signal is output at the rising edge,
100: The DE signal is output at the falling edge,
101: The DE signal is output at the falling edge,
110: The DE signal is output at the falling edge,
111: The DE signal is output at the falling edge,
Reserved
This bit is always read as 0. The write value
should always be 0.
performed.
The DE signal is output at the rising edge
of the dot clock, with the reference timing.
delayed one dot clock cycle relative to the
reference timing.
delayed two dot clock cycles relative to the
reference timing.
delayed three dot clock cycles relative to
the reference timing.
preceding the reference timing by 1/2 dot
clock cycle.
delayed 1/2 dot clock cycle relative to the
reference timing.
delayed (1+1/2) dot clock cycles relative to
the reference timing.
delayed (2+1/2) dot clock cycles relative to
the reference timing.