R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1283

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• An error in a command sequence (during data transmission) is detected through the CRC error
• Confirm there is no data busy state. Detect end of the data busy state by the data busy end flag
• Detect whether in the data busy state through the DTBUSY bit in CSTR after data transfer end
• Set the CMDOFF bit to 1 and end the command sequence.
• Set the CMDOFF bit to 1 and clear DMACR to H'00 if a CRC error (CRCERI) or a command
• Set the CMDOFF bit to 1, clear DMACR to H'00, and clear FIFO if a CRC error (CRCERI) or
Note: Access from the DMAC to FIFO must be done in bytes or words.
flag (CRCERI) or data timeout error flag. When these flags are detected, set the CMDOFF bit
in OPCR to 1, issue CMD12 (Stop Tran in SPI mode), and suspend the command sequence.
(DBSYI).
(after DRPI is detected). If still in the data busy state, wait for the DBSY flag to confirm that
the data busy state has ended.
timeout error (CTERI) occurs in the command response reception.
a data timeout error (DTERI) occurs in the write data transmission.
Rev.1.00 Jan. 10, 2008 Page 1251 of 1658
24. Multimedia Card Interface (MMCIF)
REJ09B0261-0100