R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 265

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address
array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which
association is not performed. Data field bits [31:29] are used for the virtual address specification
only in the case of a write in which association is performed.
The following three kinds of operation can be used on the IC address array:
1. IC address array read
2. IC address array write (non-associative)
3. IC address array write (associative)
Note: IC address array associative writing function may not be supported in the future SuperH
The tag and V bit are read into the data field from the IC entry corresponding to the way and
entry set in the address field. In a read, associative operation is not performed regardless of
whether the association bit specified in the address field is 1 or 0.
The tag and V bit specified in the data field are written to the IC entry corresponding to the
way and entry set in the address field. The A bit in the address field should be cleared to 0.
When a write is performed with the A bit in the address field set to 1, the tag in each way
stored in the entry specified in the address field is compared with the tag specified in the data
field. The way numbers of bits [14:13] in the address field are not used. If the MMU is enabled
at this time, comparison is performed after the virtual address specified by data field bits
[31:10] has been translated to a physical address using the ITLB. If the addresses match and
the V bit in the way is 1, the V bit specified in the data field is written into the IC entry. In
other cases, no operation is performed. This operation is used to invalidate a specific IC entry.
If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an
exception is not generated, no operation is performed, and the write is not executed.
Series. Therefore, it is recommended that the ICBI instruction should be used to operate
the IC definitely by handling ITLB miss and reporting ITLB miss exception.
Figure 8.5 Memory-Mapped IC Address Array (Cache size = 32 Kbytes)
V
A
Address field
*
: Validity bit
: Association bit
: Reserved bits (write value should be 0 and read value is undefined )
: Don't care
Data field
31
31
1 1 1 1 0 0 0 0
24
23
* * * * * * * * *
Tag
15
14
Way
13
Rev.1.00 Jan. 10, 2008 Page 233 of 1658
12
10 9
Entry
5 4 3 2 1 0
0
A
0
REJ09B0261-0100
1 0
0 0
V
8. Caches