R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1191

IC SUPERH MPU ROMLESS 436BGA

R8A77850BDBGV#RD0Z

Manufacturer Part Number
R8A77850BDBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850BDBGV#RD0Z

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850BDBGV#RD0Z
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
8
7
6
5
4
Bit Name
TXEM
RXFU
RXHA
RXEM
RXOO
Initial
Value
1
0
0
1
0
R/W
R
R
R
R
R/W*
Description
Transmit FIFO Empty Flag
This status flag is enabled only in FIFO mode. The flag
is set to 1 when the transmit FIFO is empty of data to
transmit. It is cleared to 0 when data is written to the
transmit FIFO.
If TXEM = 1 and TEIE = 1, an interrupt is generated.
Receive FIFO Full Flag
This status flag is enabled only in FIFO mode. The flag
is set to 1 when the receive FIFO is full of received
bytes and cannot accept any more. It is cleared to 0
when data is read out of the receive FIFO.
If RXFU = 1 and RFIE = 1, an interrupt is generated.
Receive FIFO Halfway Flag
This status flag is enabled only in FIFO mode. The flag
is set to 1 when the receive FIFO reaches the halfway
point, that is, it has four bytes of data and free space for
four bytes of data. This flag is cleared to 0 when the
receive data is read from receive FIFO and the data
stored in the FIFO becomes less than four bytes
(halfway point).
If RXHA = 1 and RHIE = 1, an interrupt is generated.
Receive FIFO Empty Flag
This status flag is enabled only in FIFO mode. The flag
is set to 1 when the receive FIFO is empty of received
data. It is cleared to 0 when data is written to the
receive FIFO.
If RXEM = 0 and RNIE = 1, an interrupt is generated.
Receive Buffer Overrun Occurred Flag
This status flag is set to 1 when new data has been
received but the previous received data has not been
read from SPRBR. The previously received data will not
be overwritten by the newly received data. The RXOO
flag remains set to 1 until writing 0 to this bit position.
If RXOO = 1 and ROIE = 1, an interrupt is generated.
Rev.1.00 Jan. 10, 2008 Page 1159 of 1658
23. Serial Peripheral Interface (HSPI)
REJ09B0261-0100

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