R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 817

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

17.3.1
SLPCR is a 32-bit readable/writable register that can specify transition to deep sleep mode.
SLPCR can be accessed only in longword.
This register is initialized by a power-on reset by the PRESET pin or power-on reset by WDT
overflow, or H-UDI reset.
Initial value:
Initial value:
Bit
31 to 2
1
0
R/W:
R/W:
BIt:
BIt:
Sleep Control Register (SLPCR)
Bit Name
⎯
⎯
DSLP
31
15
⎯
⎯
R
R
0
0
30
14
⎯
⎯
R
R
0
0
29
13
⎯
⎯
R
R
0
0
Initial
Value
All 0
0
0
28
⎯
12
⎯
R
R
0
0
27
⎯
11
⎯
R
R
0
0
R/W
R
R/W
R/W
26
10
⎯
⎯
R
R
0
0
25
⎯
⎯
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
These bits are always read as 0. The write value
should always be 0.
Deep Sleep
Enables transition to deep sleep mode by the SLEEP
instruction
0: Transition to sleep mode by the SLEEP instruction
1: Transition to deep sleep mode by the SLEEP
R
R
0
9
0
instruction
24
⎯
⎯
R
R
0
8
0
23
⎯
⎯
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 785 of 1658
22
⎯
⎯
R
R
0
6
0
21
⎯
⎯
R
R
0
5
0
20
⎯
⎯
R
R
0
4
0
17. Power-Down Mode
19
⎯
⎯
R
R
0
3
0
REJ09B0261-0100
18
⎯
⎯
R
R
0
2
0
R/W
17
⎯
⎯
R
0
1
0
DSLP
R/W
16
⎯
R
0
0
0