R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 18

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 PCI Controller (PCIC)
13.1 Features.............................................................................................................................. 551
13.2 Input/Output Pins............................................................................................................... 554
13.3 Register Descriptions......................................................................................................... 557
13.4 Operation ........................................................................................................................... 630
Section 14 Direct Memory Access Controller (DMAC)
14.1 Features.............................................................................................................................. 665
14.2 Input/Output Pins............................................................................................................... 667
14.3 Register Descriptions......................................................................................................... 668
14.4 Operation ........................................................................................................................... 701
Rev.1.00 Jan. 10, 2008 Page xvi of xxx
REJ09B0261-0100
12.5.11 Method for Securing Time Required for Initialization, Self-Refresh
12.5.12 Regarding the Supported Clock Ratio ................................................................ 549
12.5.13 Regarding MCKE Signal Operation ................................................................... 550
13.3.1
13.3.2
13.3.3
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
13.4.6
13.4.7
13.4.8
14.3.1
14.3.2
14.3.3
14.3.4
14.3.5
14.3.6
14.3.7
14.3.8
14.3.9
14.4.1
Cancellation, etc. ................................................................................................ 549
PCIC Enable Control Register (PCIECR) .......................................................... 562
Configuration Registers ...................................................................................... 563
PCI Local Registers ............................................................................................ 590
Supported PCI Commands ................................................................................. 630
PCIC Initialization .............................................................................................. 631
Master Access..................................................................................................... 632
Target Access ..................................................................................................... 640
Host Mode .......................................................................................................... 648
Normal Mode...................................................................................................... 651
Power Management ............................................................................................ 651
PCI Local Bus Basic Interface............................................................................ 653
DMA Source Address Registers 0 to 11 (SAR0 to SAR11)............................... 675
DMA Source Address Registers B0 to B3, B6 to B9
(SARB0 to SARB3, SARB6 to SARB9)............................................................ 676
DMA Destination Address Registers 0 to 11 (DAR0 to DAR11) ...................... 677
DMA Destination Address Registers B0 to B3, B6 to B9
(DARB0 to DARB3, DARB6 to DARB9) ......................................................... 678
DMA Transfer Count Registers 0 to 11 (TCR0 to TCR11)................................ 679
DMA Transfer Count Registers B0 to B3, B6 to B9
(TCRB0 to TCRB3, TCRB6 to TCRB9)............................................................ 680
DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11) ....................... 681
DMA Operation Register 0, 1 (DMAOR0 and DMAOR1)................................ 689
DMA Extended Resource Selectors 0 to 5 (DMARS0 to DMARS5)................. 693
DMA Transfer Requests ..................................................................................... 701
................................................................................... 551
........................................... 665