R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1495

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

29.2.2
CRR0 and CRR1 are readable/writable 32-bit registers which specify the operation to be executed
when channels 0 and 1 satisfy the match condition, respectively. The following operations can be
set in the CRR0 and CRR1 registers: (1) breaking at a desired timing for the instruction fetch cycle
and (2) requesting a break.
• CRR0
Bit
31 to 14
13
12 to 2
1
0
Initial value :
Initial value :
R/W:
R/W:
Bit :
Bit :
Match Operation Setting Registers 0 and 1 (CRR0 and CRR1)
Bit Name
—
—
—
PCB
BIE
31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
1
Initial
Value
All 0
1
All 0
0
0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R
R
R
R/W
R/W
26
10
R
R
0
0
Description
Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
Reserved
This bit is always read as 1. The write value should
always be 1.
Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
PC Break Select
Specifies either before or after instruction execution as
the break timing for the instruction fetch cycle. This bit
is invalid for breaks other than the ones for the
instruction fetch cycle.
0: Sets the PC break before instruction execution.
1: Sets the PC break after instruction execution.
Break Enable
Specifies whether or not to request a break when the
match condition is satisfied for the channel.
0: Does not request a break.
1: Requests a break.
25
R
R
0
9
0
24
R
R
0
8
0
23
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 1463 of 1658
22
R
R
6
0
0
21
R
R
0
5
0
29. User Break Controller (UBC)
20
R
R
0
4
0
19
R
R
0
3
0
REJ09B0261-0100
18
R
R
0
2
0
PCB
R/W
17
R
0
1
0
R/W
BIE
16
R
0
0
0