R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1321

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

25.5.3
The HAC supports DMA transfer for slots 3 and 4 of both the RX and TX frames. Specify the slot
data size for DMA transfer, 16 or 20 bits, with the DMARX16 and DMATX16 bits in HACACR.
When the data size is 20 bits, transfer of data slots 3 and 4 requires two local bus access cycles.
Since each of the receiver and transmitter has its DMA request, the stereo mode generates a DMA
request for slots 3 and 4 separately. The mono mode generates a DMA request for just one slot.
When the data size is 16 bits, data from slots 3 and 4 are packed into a single 32-bit quantity (left
data and right data are in PCML), which requires only one local bus access cycle.
It may be necessary to halt a DMA transfer before the end count is reached, depending on system
applications. If so, clear the corresponding DMA bit in HACACR to 0 (DMA disabled). To
resume a DMA transfer, reprogram the DMAC and then set the corresponding DMA bit to 1
(DMA enabled).
25.5.4
Interrupts can be used for flag events from the receiver and transmitter. Make the setting for each
interrupt in the corresponding interrupt enable register. Interrupts include a request to the CPU to
read/write slot data, overrun and underrun. To get the interrupt source, read the status register.
Writing 0 to the bit will clear the corresponding interrupt.
DMA
Interrupts
Rev.1.00 Jan. 10, 2008 Page 1289 of 1658
25. Audio Codec Interface (HAC)
REJ09B0261-0100