R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1227

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

24.3.9
TBCR is an 8-bit readable/writable register that specifies the number of bytes to be transferred
(block size) for each single block transfer command. TBCR specifies the number of data block
bytes not including the start bit, end bit, and CRC.
The multiple block transfer command corresponds to the number of bytes of each data block. This
setting is ignored by the stream transfer command.
Bit
7 to 4
3
2
1
0
Transfer Byte Number Count Register (TBCR)
Bit Name
—
CS3
CS2
CS1
CS0
Initial value:
Initial
Value
All 0
0
0
0
0
R/W:
Bit:
⎯
7
0
R
R/W
R
R/W
R/W
R/W
R/W
⎯
R
6
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Transfer Data Block Size
Four or more bytes should be set before executing a
command with data transfer.
0000: 1 byte (for forced erase)
0001: 2 bytes
0010: 4 bytes
0011: 8 bytes
0100: 16 bytes
0101: 32 bytes
0110: 64 bytes
0111: 128 bytes
1000: 256 bytes
1001: 512 bytes
1010: 1024 bytes
1011: 2048 bytes
1100 to 1111: Setting prohibited
⎯
R
5
0
⎯
4
0
R
R/W
C3
3
0
Rev.1.00 Jan. 10, 2008 Page 1195 of 1658
R/W
C2
2
0
24. Multimedia Card Interface (MMCIF)
R/W
C1
1
0
R/W
C0
0
0
REJ09B0261-0100