R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 524

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

12. DDR2-SDRAM Interface (DBSC2)
12.4.6
The SDRAM timing register 1 (DBTR1) is a readable/writable register. It is initialized only upon
power-on reset.
Initial value:
Initial value:
Rev.1.00 Jan. 10, 2008 Page 492 of 1658
REJ09B0261-0100
Bit
31 to 19 ⎯
18 to 16 TRP2 to
R/W:
R/W:
BIt:
BIt:
SDRAM Timing Register 1 (DBTR1)
Bit Name
TRP0
31
15
⎯
⎯
R
R
0
0
30
14
⎯
⎯
R
R
0
0
29
⎯
13
⎯
R
Initial
Value
All 0
001
R
0
0
28
12
⎯
⎯
R
R
0
0
27
11
⎯
⎯
R
R
0
0
R/W
R
R/W
TRRD2
R/W
26
10
⎯
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
tRP (PRE-ACT/REF period) Setting Bits
These bits set the PRE-ACT minimum period constraint
for the same bank. These bits should be set according
to the DDR2-SDRAM specifications. The number of
cycles is the number of DDR clock cycles.
000: Setting prohibit (If specified, correct operation
001: 2 cycles
010: 3 cycles
011: 4 cycles
100: 5 cycles
101: Setting prohibit (If specified, correct operation
111: Setting prohibit (If specified, correct operation
TRRD1
:
R/W
25
⎯
R
0
9
0
cannot be guaranteed.)
cannot be guaranteed.)
cannot be guaranteed.)
TRRD0
R/W
24
⎯
R
0
8
0
23
⎯
⎯
R
R
0
7
0
22
⎯
⎯
R
R
0
6
0
21
⎯
⎯
R
R
0
5
0
20
⎯
⎯
R
R
0
4
0
19
⎯
⎯
R
R
0
3
0
TWR2
TRP2
R/W
R/W
18
0
0
2
TWR1
TRP1
R/W
R/W
17
0
1
0
TWR0
TRP0
R/W
R/W
16
1
0
1