R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 523

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Notes: 1. AL (Additive Latency) supported by the DBSC2 is only 0.
Bit
2 to 0
2. Writing to this register should be performed only when the following conditions are met.
Bit Name
TRCD2 to
TRCD0
•
•
When SDRAM access is disabled (when the ACEN bit in the DBEN register is 0.).
When automatic issue of auto-refresh is disabled (when the ARFEN bit in the
DBRFCNT0 register is cleared to 0.).
Initial
Value
001
R/W
R/W
Description
These bits set the ACT-READ/WRITE minimum period.
These bits should be set according to the DDR2-
SDRAM specifications. The number of cycles is the
number of DDR clock cycles.
000: Setting prohibit (If specified, correct operation
001: 2 cycles
010: 3 cycles
011: 4 cycles
100: 5 cycles
101: Setting prohibit (If specified, correct operation
111: Setting prohibit (If specified, correct operation
tRCD (ACT-READ/WRITE period) Setting Bits
:
cannot be guaranteed.)
cannot be guaranteed.)
cannot be guaranteed.)
Rev.1.00 Jan. 10, 2008 Page 491 of 1658
12. DDR2-SDRAM Interface (DBSC2)
REJ09B0261-0100