R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1259

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(6)
Flash memory operation commands include a number of commands involving write data. Such
commands confirm the card status by the command argument and command response, and
transmit card information and flash memory data via the MMCDAT pin. For a command that is
related to time-consuming processing such as flash memory write, the card indicates the data busy
state via the MMCDAT pin.
In multiple block transfer, two transfer methods can be used; one is open-ended and the other is
pre-defined. Open-ended operation is suspended for each block transfer and an instruction to
continue or end the command sequence is waited for. For pre-defined operation, the block number
of the transmission is set before transfer.
When the FIFO is full between blocks in multiple block transfer, the command sequence is
suspended. Once the command sequence is suspended, process the data in FIFO if necessary
before allowing the command sequence to continue.
Figures 24.15 to 24.18 show examples of the command sequence for commands with write data.
Figures 24.19 to 24.21 show the operational flows for commands with write data.
• Make settings to issue a command, and clear FIFO.
• Set the CMDSTART bit in CMDSTRT to 1 to start command transmission. MMCCMD must
• Command transmission completion can be confirmed by the command transmit end interrupt
• The command response is received from the card.
• If the card returns no command response, the command response is detected by the command
• Set the write data to FIFO.
• Set the DATAEN bit in OPCR to 1 to start write data transmission. MMCDAT must be kept
• Inter-block suspension in multiple block transfer and suspension according to the FIFO empty
be kept driven until the end bit output is completed.
(CMDI).
timeout error (CTERI).
driven until the end bit output is completed.
are detected by the data response interrupt (DRPI) and FIFO empty interrupt (FEI),
respectively. To continue the command sequence, set the next data to FIFO and set the
DATAEN bit in OPCR to 1. To end the command sequence, set the CMDOFF bit in OPCR to
1 and issue CMD12. Unless the sequence is suspended in pre-defined multiple block transfer,
CMD12 is not needed.
Commands with Write Data
Rev.1.00 Jan. 10, 2008 Page 1227 of 1658
24. Multimedia Card Interface (MMCIF)
REJ09B0261-0100