R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1169

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22.4.6
(1)
The transmit and receive FIFO systems of the SIOF have the following features.
• 16-stage 32-bit FIFOs for transmission and reception
• The FIFO pointer can be updated in one read or write cycle regardless of access size of the
(2)
The transfer request of the FIFO can be issued to the CPU or DMAC as the following interrupt
sources.
• FIFO transmit request: TDREQ (transmit interrupt source)
• FIFO receive request: RDREQ (receive interrupt source)
The request conditions for FIFO transmit or receive can be specified individually. The request
conditions for the FIFO transmit and receive are specified by the TFWM2 to TFWM0 bits and the
bits RFWM2 to RFWM0 in SIFCTR, respectively. Tables 22.11 and 22.12 summarize the
conditions to issue transmit request and those to issue receive request, respectively.
Table 22.11 Conditions to Issue Transmit Request
Notes: 1. The number of requested stages is the number of stages in transmit/receive FIFO.
TFWM2 to
TFWM0
000
100
101
110
111*
CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.)
2
Overview
Transfer Request
2. Setting prohibited in DMA use.
FIFO
Number of
Requested Stages*
1
4
8
12
16
1
Transmit Request
Empty area is 16 stages
Empty area is 12 stages or more
Empty area is 8 stages or more
Empty area is 4 stages or more
Empty area is 1 stage or more
Rev.1.00 Jan. 10, 2008 Page 1137 of 1658
22. Serial I/O with FIFO (SIOF)
REJ09B0261-0100
Used Areas
Smallest
Largest