R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 426

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

11. Local Bus State Controller (LBSC)
Table 11.12 64-Bit External Device/Little Endian Access and Data Alignment (2)
Note:
Rev.1.00 Jan. 10, 2008 Page 394 of 1658
REJ09B0261-0100
Access
Size
Byte
Word
Longword
32 Bytes* 8n
Operation
*
Address No. WE7
8n
8n + 1
8n + 2
8n + 3
8n + 4
8n + 5
8n + 6
8n + 7
8n
8n + 2
8n + 4
8n + 6
8n
8n + 4
8n + 8
8n + 16
8n + 24
This table shows an example when the access start address is on the 32-byte
boundary. When the start address is not on the 32-byte boundary, accesses are
performed up to immediately before the 32-byte boundary and the address is wrapped
around to the previous 32-byte boundary.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
3
4
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Asserted ⎯
⎯
⎯
⎯
Asserted Asserted ⎯
⎯
Asserted Asserted Asserted Asserted ⎯
Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted
WE6
⎯
⎯
⎯
⎯
⎯
⎯
Asserted ⎯
⎯
⎯
⎯
⎯
WE5
⎯
⎯
⎯
⎯
⎯
Asserted ⎯
⎯
⎯
⎯
Asserted Asserted ⎯
⎯
⎯
⎯
⎯
⎯
Asserted ⎯
⎯
⎯
⎯
⎯
⎯
⎯
WE4
Strobe Signal
WE3
⎯
⎯
⎯
Asserted ⎯
⎯
⎯
⎯
⎯
Asserted Asserted ⎯
⎯
Asserted Asserted Asserted Asserted
⎯
⎯
Asserted ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
WE2
WE1
⎯
Asserted ⎯
⎯
⎯
⎯
⎯
⎯
Asserted Asserted
⎯
⎯
⎯
Asserted
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
WE0
⎯