R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1140

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. Serial I/O with FIFO (SIOF)
22.3.3
SITDR is a 32-bit write-only register that specifies SIOF transmit data.
Rev.1.00 Jan. 10, 2008 Page 1108 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 16 SITDL[15:0]
15 to 0
R/W:
R/W:
BIt:
BIt:
Transmit Data Register (SITDR)
Bit Name
SITDR[15:0]
31
15
—
W
—
W
30
—
14
—
W
W
29
—
13
—
W
W
Initial
Value
Undefined
Undefined
28
12
—
—
W
W
27
11
—
—
W
W
R/W
W
W
26
10
—
W
—
W
Description
Left-Channel Transmit Data
These bits specify data to be output from the
SIOF_TXD pin as left-channel data. The position of the
left-channel data in the transmit frame depends on the
value set in the TDLA bit in SITDAR.
•
Right-Channel Transmit Data
These bits specify data to be output from the
SIOF_TXD pin as right-channel data. The position of
the right-channel data in the transmit frame depends on
the value set in the TDRA bit in SITDAR.
•
25
—
W
—
W
9
These bits are valid when the TDLE bit in SITDAR is
set to 1.
These bits are valid when the TDRE bit in SITDAR
is set to 1, and the TLREP bit in SITDAR is cleared
to 0.
SITDR[15:0]
SITDL[15:0]
24
—
W
—
W
8
23
—
W
—
W
7
22
—
W
—
W
6
21
—
—
W
W
5
20
—
—
W
W
4
19
—
—
W
W
3
18
—
W
—
W
2
17
—
W
—
W
1
16
—
W
—
W
0