R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1589

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Module
Name
HAC
SSI
FLCTL
Name
Command/status data register 1
PCM left channel register 1
PCM right channel register 1
TX interrupt enable register 1
TX status register 1
RX interrupt enable register 1
RX status register 1
HAC control register 1
Control register 0
Status register 0
Transmit data register 0
Receive data register 0
Control register 1
Status register 1
Transmit data register 1
Receive data register 1
Common control register
Command control register
Command code register
Address register
Data register
Data counter register
Interrupt DMA control register
Ready busy timeout setting register FLBSYTMR H'0000 0000
Ready busy timeout counter
Data FIFO register
Control code FIFO register
Transfer control register
Address register 2
Abbrev.
HACCSDR1
HACPCML1 H'0000 0000
HACPCMR1
HACTIER1
HACTSR1
HACRIER1 H'0000 0000
HACRSR1
HACACR1
SSICR0
SSISR0
SSITDR0
SSIRDR0
SSICR1
SSISR1
SSITDR1
SSIRDR1
FLCMNCR
FLCMDCR
FLCMCDR
FLADR
FLDATAR
FLDTCNTR H'0000 0000
FLINTDMACR
FLBSYCNT H'0000 0000
FLDTFIFO
FLECFIFO
FLTRCR
FLADR2
Power-on
Reset by
PRESET Pin/
WDT/H-UDI
H'0000 0000
H'0000 0000
H'0000 0000
H'F000 0000
H'0000 0000
H'0200 0003
H'0000 0000
H'0000 0000
H'0200 0003
H'0000 0000
H'0000 0000
Undefined
H'0000 0000
H'8400 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
Undefined
H'00
H'0000 0000
Rev.1.00 Jan. 10, 2008 Page 1557 of 1658
Manual Reset
by
WDT/Multiple
Exception
H'0000 0000
H'0000 0000
H'F000 0000
H'0000 0000
H'0200 0003
H'0000 0000
H'0000 0000
H'0000 0000
H'0200 0003
H'0000 0000
H'0000 0000
H'0000 0000
Undefined
Undefined
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'8400 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'00
H'0000 0000
Sleep/
Deep Sleep by
SLEEP
Instruction
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
REJ09B0261-0100
31. Register List
Module
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained