R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1381

IC SUPERH MPU ROMLESS 436BGA

R8A77850BDBGV#RD0Z

Manufacturer Part Number
R8A77850BDBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850BDBGV#RD0Z

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850BDBGV#RD0Z
Manufacturer:
Renesas Electronics America
Quantity:
10 000
27.3.4
FLADR is a 32-bit readable/writable register that specifies an address to be output in command
access mode. In sector access mode, a physical sector number specified in the physical sector
address bits is converted into an address to be output.
• Command access mode
Initial value:
Initial value:
Bit
31 to 24 ADR[31:24] H'00
23 to 16 ADR[23:16] H'00
15 to 8
7 to 0
R/W:
R/W:
Bit:
Bit:
Address Register (FLADR)
Bit Name
ADR[7:0]
ADR[15:8]
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
H'00
H'00
ADR[31:24]
R/W
R/W
ADR[15:8]
28
12
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
27
11
0
0
R/W
R/W
26
10
0
0
Description
Fourth Address Data
Specify the fourth data to be output to flash memory as
an address in command access mode.
Third Address Data
Specify the third data to be output to flash memory as
an address in command access mode.
Second Address Data
Specify the second data to be output to flash memory
as an address in command access mode.
First Address Data
Specify the first data to be output to flash memory as an
address in command access mode.
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
R/W
R/W
23
0
7
0
27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1349 of 1658
R/W
R/W
22
6
0
0
R/W
R/W
21
0
5
0
ADR[23:16]
R/W
R/W
ADR[7:0]
20
0
4
0
R/W
R/W
19
0
3
0
REJ09B0261-0100
R/W
R/W
18
0
2
0
R/W
R/W
17
1
0
0
R/W
R/W
16
0
0
0

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