AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 15

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

REV. 0
lock loops, which can be arbitrarily assigned to the conversion
resources. The lock range of these digital PLLs is 4 kHz to
54 kHz, which is the same range supported by the register-
controlled clock generators.
If a SYNC input stops after its associated phase lock loop has
had a chance to initially lock, the AD1843 will continue to gen-
erate a sample clock (as well as BIT clock and CONV clock)
very similar to the initial frequency, but off by at most 1%.
The three SYNC inputs feed three on-chip Digital Phase Lock
Loops (DPLLs) which utilize a first-order loop filter with a
20 Hz corner frequency. Jitter frequencies above 20 Hz are
attenuated, and jitter frequencies below 20 Hz are interpreted as
time base drift, and are tracked. The DPLL provides 12 dB per
octave of jitter rejection. The DPLLs have been designed to tol-
erate at least 2% Unit Interval (UI) of SYNC clock jitter. The
DPLLs are critically damped at all input frequencies.
Power Management
The AD1843 SoundComm codec has extensive power manage-
ment capabilities. Hardware power down is performed using the
PWRDWN pin. Software power management is programmed us-
ing Control Register Address 27 and 28. Several elements of the
AD1843 can be powered down on a selective basis. These blocks
include: the DAC2 to DAC1 analog mixer; the entire DAC1 con-
version channel; the entire DAC2 conversion channel; the analog
half of the ADC, DAC1 and DAC2; the headphone driver; the en-
tire analog mixer; the right ADC channel; the left ADC channel; all
+5 V Digital, +5 V Analog Supplies
Software Power Down
CLKOUT Output
All Bit Clocks and
All Conversion Clocks
Clock Generator 1
Clock Generator 2
Clock Generator 3
All Clock Generators
Headphone Driver
DAC2 to DAC1 Mix
Analog Input to Analog Output Mix
ADC Left Channel
ADC Right Channel
ADC Left and Right Channels
DAC2 (Left and Right Channels)
DAC1 (Left and Right Channels)
DAC2 AND DAC1 (Left and Right Chs)
ADC and DAC2 and DAC1
Analog Channel
All Control Register 27
Converter
All of the Above (Register 27 and
Clocks and PDNI)
Total Active Operation Current: 200 mA
Control Register Bit(s)
ENCLKO Bit = 0
ENBT3, ENBT2, ENBT1 Bits = 0
ENCV3, ENCV2, ENCV1 Bits = 0
C1EN Bit = 0
C2EN Bit = 0
C3EN Bit = 0
C1EN, C2EN, C3EN Bits = 0
HPEN Bit = 0
DDMEN Bit = 0
AAMEN Bit = 0
ADLEN Bit = 0
ADREN Bit = 0
ADLEN, ADREN Bits = 0
DA2EN Bit = 0
DA1EN Bit = 0
DA2EN, DA1EN Bits = 0
ADLEN, ADREN,
DA2EN, DA1EN Bits = 0
ANAEN Bit = 0
HPEN, DDMEN, AAMEN, ADLEN,
ADREN, DA2EN, DA1EN, ANAEN Bits = 0
PDNI Bit = 1
ENCLKO, ENBT3, ENBT2, ENBT1, ENCV3,
ENCV2, ENCV1, C1EN, C2EN, C3EN, HPEN,
DDMEN, AAMEN, ADLEN, ADREN, DA2EN,
DA1EN, ANAEN Bits = 0, PDNI Bit = 1
Table I. AD1843 Power-Down Savings
–15–
four conversion channels; clock generator 1; clock generator 2;
clock generator 3; conversion clock outputs 1 through 3; bit clock
outputs 1 through 3; and the nominal 24.576 MHz clock output.
Refer to the descriptions of Control Register Address 27 and 28 for
further information.
For proper operation, the AD1843 must be calibrated following
power-up. This initial calibration occurs automatically without any
user intervention or programming. Subsequent to this initial
power-up autocalibration, there is no requirement to recalibrate the
SoundComm codec following software power-down sequences.
The entire AD1843 or selected portions of the device may be
powered down, allowed to idle indefinitely, then powered up
and used immediately, without the need for repeated auto-
calibration. The digital information obtained during the initial
power-up calibration is retained and valid unless the RESET or
PWRDWN pin is asserted, forcing a hardware reset. (If desired,
the user can specify that a calibration cycle occur when leaving
the software power-down state by setting ACEN (Control Reg-
ister Address 28, Bit 14) to ”1.”) A hardware reset or power-
down clears the calibration information, and therefore a fresh
autocalibration cycle is performed by the AD1843 following this
event. Autocalibration takes approximately 4 ms to complete.
The following table provides an indication of the power savings
associated with powering-down the various resources in the
AD1843. Note that the power savings is somewhat order-
Average, Typical
Absolute I
I
8 mA
2 mA
6 mA
6 mA
6 mA
20 mA
8 mA
2 mA
8 mA
8 mA
8 mA
38 mA
30 mA
24 mA
60 mA
108 mA
54 mA
134 mA
140 mA
176 mA
CC
Current
DD
+
Average, Typical
Normalized
Power Savings
4%
1%
3%
3%
3%
10%
4%
1%
4%
4%
4%
17%
15%
12%
30%
54%
27%
67%
88%
70%
AD1843