AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 50

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

AD1843
C2EN
C1EN
ENCLKO
XCTL1:0
ENCV3
ENBT3
ENCV2
ENBT2
ENCV1
ENBT1
LINRSD
LINLSD
res
res
Address 29
Data 15
Data 7
res
res
CLKOUT Pin Enable.
External Control. The state of these independent bits is reflected on the respective XCTL1 and XCTL0 output pins.
CONV3 Pin Enable.
BIT3 Pin Enable.
CONV2 Pin Enable.
BIT2 Pin Enable.
CONV1 Pin Enable.
BIT1 Pin Enable.
Line Input Right Channel Single-Ended or Differential Configuration.
Line Input Left Channel Single-Ended or Differential Configuration.
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Clock Generator 2 Enable/Power Down.
0 = Clock Generator 2 Powered Down
1 = Clock Generator 2 Enabled
Clock Generator 1 Enable/Power Down.
0 = Clock Generator 1 Powered Down
1 = Clock Generator 1 Enabled
0 = Clock Output is Three-stated (Powered Down)
1 = Clock Output is Enabled
0 = TTL Logic Level LO on XCTL1/XCTL0 pin
1 = TTL Logic Level HI on XCTL1/XCTL0 pin
0 = CONV3 is Three-stated (Powered Down)
1 = CONV3 is Enabled
0 = BIT3 is Three-stated (Powered Down)
1 = BIT3 is Enabled
0 = CONV2 is Three-stated (Powered Down)
1 = CONV2 is Enabled
0 = BIT2 is Three-stated (Powered Down)
1 = BIT2 is Enabled
0 = CONV1 is Three-stated (Powered Down)
1 = CONV1 is Enabled
0 = BIT1 is Three-stated (Powered Down)
1 = BIT1 is Enabled
0 = Right Channel Line Input is Single-Ended
1 = Right Channel Line Input is Differential
0 = Left Channel Line Input is Single-Ended
1 = Left Channel Line Input is Differential
Initial default state after reset: 1100 0100 0000 0000 (C400 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.
Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.
Data 14
Data 6
res
res
Reserved for Future Expansion
Data 13
Data 5
res
res
Data 12
Data 4
res
res
–50–
Data 11
Data 3
res
res
Data 10
Data 2
res
res
Data 9
Data 1
res
res
Data 8
Data 0
res
res
REV. 0