AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 40

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

AD1843
res
C2REF
C2VID
C2PLLG
C2P200
C2X8/7
C2C128
res
C2M7:0
Address 19
Data 15
C2REF
Data 7
C2M7
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Clock Generator 2 Reference Select. Selects the fundamental clock reference used by Clock Generator 2 to
Clock Generator 2 Video Lock Mode. This bit is used to select between lock modes when the Clock Generator 2 is
Clock Generator 2 PLL Loop Gain Select. If reset to “0,” this bit selects finite PLL loop gain, and if set to “1,” this
Clock Generator 2 Bit Clock +200 Frequency Modifier. When set to “1,” the Bit clock driven out of pin BIT2 will
Clock Generator 2 Conversion Clock 8/7 Frequency Modifier. When set to “1,” the Conversion clock frequency gen-
Clock Generator 2 Conversion Clock Pin (CONV2) Frequency Select. When set to “1,” the frequency driven on to
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Clock Generator 2 Clock Rate Modifiers.
Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; or when the G1EN bit in Control Register
Address 28 is reset to “0” (clock generator 1 disabled).
synthesize its “Conversion” (sample) and “Bit” clock rates.
0 = Clocks are referenced to the input on pin XTALI (crystal or master clock input).
1 = Clocks are referenced to the input on pin SYNC2 (Sync 2 Clock Input).
referenced to SYNC2 (C2REF set to “1”). This bit should be reset to “0” if C2REF is reset to “0.” When reset to
“0,” Clock Generator 2 is in normal lock mode where the Conversion clock will be frequency and phase locked to
SYNC2, and the Bit clock frequency is chosen using bits C2M7:0 and C2P200. When set to “1,” Clock Generator 2
is in video lock mode, where the Conversion clock frequency is selected using bits C2M7:0, and a Bit clock is not produced.
bit selects infinite PLL loop gain. This bit should nominally be reset to “0.” Setting it to “1” may enhance the PLL’s
ability to lock to certain SYNC2 inputs, but it may also increase conversion noise.
have a frequency that is 200 Hertz greater than the frequency selected through bit C2M7:0. This bit is ignored when
in Video Lock Mode (C2VID set to “1”). C2P200 only modifies the bit clock driven on the BIT2 pin.
erated will be 8/7 times the value programmed in Control Register Address 20. This bit is ignored when clocks are
referenced to SYNC2 (C2REF set to “1”).
the CONV2 pin will be 128 times the conversion rate. When reset to “0,” the frequency driven on to the CONV2 pin
will be the same as the conversion rate. C2C128 only modifies the clock frequency driven on the CONV2 pin.
When not in Video Lock Mode (C2REF and C2VID are not both set to “1”):
Bits C2M7:0 select the Bit clock rate which will be driven out on pin BIT2. Using the following table, the least sig-
nificant four bits (C2M3:0) are programmed to the desired Bit clock rate, and the most significant four bits
overwritten even if all previously programmed phase advance/retard has not been processed. When written, the con-
tents of this register (just prior to the write) are transmitted during slot 1 of the following frame (as with all Control
Register writes).
Sample clock frequency is defined by Control Register Address 20 and Bit C2X8/7.
Sample clock phase may be shifted by Control Register Address 21.
Bit clock frequency is defined by bits C2M7:0 and C2P200.
Bit C2VID is ignored.
Sample clock frequency is defined by C2VID and C2M7:0.
Sample clock phase is locked to SYNC2 and cannot be shifted.
Bit clock frequency is defined by bits C2M7:0 and C2P200 unless in Video Lock Mode (C2VID set to “1”)
where the Bit clocks are not produced.
Control Register Addresses 17, 18 and the C2X8/7 bit are ignored.
Data 14
C2VID
Data 6
C2M6
Clock Generator 2 Control—Mode
C2PLLG
Data 13
Data 5
C2M5
Data 12
C2P200
Data 4
C2M4
–40–
Data 11
C2X8/7
Data 3
C2M3
Data 10
C2C128
Data 2
C2M2
Data 9
Data 1
C2M1
res
Data 8
Data 0
C2M0
res
REV. 0