AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 52

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

AD1843
Figure 16 shows an annotated version of the AD1843 detailed
block diagram, indicating the specific Control Register bit fields
which configures the various features of the SoundComm codec.
START-UP SEQUENCE
The following paragraphs describe a typical, generic start-up
sequence, for the purpose of helping hardware, systems and
software driver engineers understand some of the considerations
involved in bringing up a system which includes the AD1843.
Note that it does not exhaustively outline all of the flexible con-
figurations and features available in the AD1843.
1. System power supplies stabilize. Ideally, the AD1843
2. Assert the RESET signal (PLCC Pin 52, TQFP Pin 65).
3. Deassert the RESET signal and enter a wait period to
CONTROL REG
ADDRESS 12
ADDRESS 13
ADDRESS 14
ADDRESS 15
ADDRESS 16
ADDRESS 17
ADDRESS 18
ADDRESS 19
ADDRESS 20
ADDRESS 21
ADDRESS 22
ADDRESS 23
ADDRESS 24
ADDRESS 25
ADDRESS 26
ADDRESS 27
ADDRESS 28
ADDRESS 29
ADDRESS 30
ADDRESS 31
ADDRESS 10
ADDRESS 11
ADDRESS 0
ADDRESS 1
ADDRESS 2
ADDRESS 3
ADDRESS 4
ADDRESS 5
ADDRESS 6
ADDRESS 7
ADDRESS 8
ADDRESS 9
RESET pin should be held LO during this period. If
RESET is not asserted, the AD1843 will come up in an un-
known state.
Once the power supplies have stabilized, the AD1843 RE-
SET must be asserted LO for at least 100 ns with BM
(PLCC Pin 10, TQFP Pin 12) tied to the appropriate level to
establish whether the codec is serial bus master or slave.
allow the AD1843 internal clocks and the external crys-
tal oscillator to stabilize. The wait period duration will be
typically 400 s to 800 s after RESET is deasserted, but sig-
nificantly longer time may be necessary depending on
XTALI and XTALO pin parasitics. If the AD1843 is serial
bus master, the host CPU or DSP can poll the INIT bit
(Control Register Address 0, Bit 15) to determine when the
AD1843 is ready to proceed. Alternatively, the host CPU or
DSP can write to Control Register 16 through 24, or 26 or
28 (using a data pattern different from the initial reset default
for that Control Register), and proceed when the Control
DATA 15
INIT
RES
LSS2
LD1MM
LX1MM
LX2MM
LX3MM
LMCMM
MNMM
LDA1GM
LDA2GM
LDA1AM
LDA2AM
LAD1MM
LAD2MM
RES
C1REF
C1C15
RES
C2REF
C2C15
RES
C3REF
C3C15
RES
DRSFLT
DA2SM
DFREE
PDNI
RES
RES
RES
DATA 14
PDNO
RES
LSS1
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
C1VID
C1C14
RES
C2VID
C2C14
RES
C3VID
C3C14
RES
DAMIX
DA1SM
RES
ACEN
RES
RES
RES
DATA 13
RES
RES
LSS0
RES
RES
RES
RES
RES
RES
LDA1G5
LDA2G5
LDA1A5
LDA2A5
LAD1M5
LAD2M5
RES
C1PLLG
C1C13
RES
C2PLLG
C2C13
RES
C3PLLG
C3C13
RES
RES
RES
RES
C3EN
RES
RES
RES
DATA 12
RES
RES
LMGE
LD1M4
LX1M4
LX2M4
LX3M4
LMCM4
MNM4
LDA1G4
LDA2G4
LDA1A4
LDA2A4
LAD1M4
LAD2M4
RES
C1P200
C1C12
RES
C2P200
C2C12
RES
C3P200
C3C12
RES
RES
RES
DDMEN
C2EN
RES
RES
RES
DATA 11
RES
RES
LIG3
LD1M3
LX1M3
LX2M3
LX3M3
LMCM3
MNM3
LDA1G3
LDA2G3
LDA1A3
LDA2A3
LAD1M3
LAD2M3
DA2C1
C1X8/7
C1C11
RES
C2X8/7
C2C11
RES
C3X8/7
C3C11
RES
RES
DA2F1
RES
C1EN
RES
RES
RES
Figure 15. AD1843 Control Register Map
DATA 10
RES
RES
LIG2
LD1M2
LX1M2
LX2M2
LX3M2
LMCM2
MNM2
LDA1G2
LDA2G2
LDA1A2
LDA2A2
LAD1M2
LAD2M2
DA2C0
C1C128
C1C10
RES
C2C128
C2C10
RES
C3C128
C3C10
RES
RES
DA2F0
RES
ENCLKO
RES
RES
RES
DATA 9
RES
SU2
LIG1
LD1M1
LX1M1
LX2M1
LX3M1
LMCM1
MNM1
LDA1G1
LDA2G1
LDA1A1
LDA2A1
LAD1M1
LAD2M1
DA1C1
RES
C1C9
RES
RES
C2C9
RES
RES
C3C9
RES
DA2FLT
DA1F1
DA2EN
XCTL1
RES
RES
RES
–52–
DATA 8
RES
SU1
LIG0
LD1M0
LX1M0
LX2M0
LX3M0
LMCM0
MNM0
LDA1G0
LDA2G0
LDA1A0
LDA2A0
LAD1M0
LAD2M0
DA1C0
RES
C1C8
C1PD
RES
C2C8
C2PD
RES
C3C8
C3PD
DA1FLT
DA1F0
DA1EN
XCTL0
RES
RES
RES
4. Put the conversion resources into standby. With the ex-
Register readback (on the following frame) matches the data
written. Writes to these Control Registers will fail until the
AD1843 internal clocks are stabilized. If the system has been
designed for 16 slots per frame, it is suggested that this first
“polling write/readback” is to Control Register Address 26,
with FRS (Bit 6) set to “1” and FRST (Bit 5) set to “1,”
so that the AD1843 will support the 16 slot per frame mode
immediately.
ception of the serial interface, the AD1843 is still completely
powered down before this step. The PDNI bit (Control Reg-
ister Address 28, Bit 15) should now be reset to “0” to ini-
tiate the process of taking the AD1843 conversion resources
out of power down and into standby. This requires approxi-
mately 470 ms. An autocalibration cycle always occurs
(automatically, without user programming or intervention)
following the deassertion of the RESET pin or the
PWRDWN pin (i.e., hardware reset or hardware power
down), adding another approximately 4 ms, for a total of
approximately 474 ms. Subsequent software power-down
cycles, programmed using Control Register bits, do not ordi-
narily require additional calibration cycles. The original cali-
bration information is retained during the power down
sequence. However, the user can force an autocalibration to
occur following a software power down by setting ACEN
(Control Register Address 28, Bit 14) to “1.” The host CPU
or DSP can poll the PDNO bit (Control Register Address 0,
Bit 14) to determine when the conversion resources are out
of power down. Alternatively, the host CPU or DSP can
write to Control Register Address 27 (using a data pattern
different from the initial reset default), and proceed when the
DATA 7
RES
RES
RSS2
RD1MM
RX1MM
RX2MM
RX3MM
RMCMM
ALLMM
RDA1GM
RDA2GM
RDA1AM
RDA2AM
RAD1MM
RAD2MM
RES
C1M7
C1C7
C1P7
C2M7
C2C7
C2P7
C3M7
C3C7
C3P7
DAADR1
SCF
ANAEN
ENCV3
RES
RES
RES
DATA 6
RES
RES
RSS1
RES
RES
RES
RES
RES
MNOM
RES
RES
RES
RES
RES
RES
RES
C1M6
C1C6
C1P6
C2M6
C2C6
C2P6
C3M6
C3C6
C3P6
DAADR0
FRS
HPEN
ENBT3
RES
RES
RES
DATA 5
RES
RES
RSS0
RES
RES
RES
RES
RES
HPOM
RDA1G5
RDA2G5
RDA1A5
RDA2A5
RAD1M5
RAD2M5
RES
C1M5
C1C5
C1P5
C2M5
C2C5
C2P5
C3M5
C3C5
C3P5
DAADL1
FRST
RES
ENCV2
RES
RES
RES
DATA 4
RES
RES
RMGE
RD1M4
RX1M4
RX2M4
RX3M4
RMCM4
HPOS
RDA1G4
RDA2G4
RDA1A4
RDA2A4
RAD1M4
RAD2M4
RES
C1M4
C1C4
C1P4
C2M4
C2C4
C2P4
C3M4
C3C4
C3P4
DAADL0
ADTLK
AAMEN
ENBT2
RES
RES
RES
DATA 3
ID3
OVR1
RIG3
RD1M3
RX1M3
RX2M3
RX3M3
RMCM3
SUMM
RDA1G3
RDA2G3
RDA1A3
RDA2A3
RAD1M3
RAD2M3
ADRC1
C1M3
C1C3
C1P3
C2M3
C2C3
C2P3
C3M3
C3C3
C3P3
RES
ADRF1
RES
ENCV1
RES
RES
RES
DATA 2
ID2
OVR0
RIG2
RD1M2
RX1M2
RX2M2
RX3M2
RMCM2
RES
RDA1G2
RDA2G2
RDA1A2
RDA2A2
RAD1M2
RAD2M2
ADRC0
C1M2
C1C2
C1P2
C2M2
C2C2
C2P2
C3M2
C3C2
C3P2
RES
ADRF0
RES
ENBT1
RES
RES
RES
DATA 1
ID1
OVL1
RIG1
RD1M1
RX1M1
RX2M1
RX3M1
RMCM1
DAC2T
RDA1G1
RDA2G1
RDA1A1
RDA2A1
RAD1M1
RAD2M1
ADLC1
C1M1
C1C1
C1P1
C2M1
C2C1
C2P1
C3M1
C3C1
C3P1
ADRFLT
ADLF1
ADREN
LINRSD
RES
RES
RES
DATA 0
ID0
OVL0
RIG0
RD1M0
RX1M0
RX2M0
RX3M0
RMCM0
DAC1T
RDA1G0
RDA2G0
RDA1A0
RDA2A0
RAD1M0
RAD2M0
ADLC0
C1M0
C1C0
C1P0
C2M0
C2C0
C2P0
C3M0
C3C0
C3P0
ADLFLT
ADLF0
ADLEN
LINLSD
RES
RES
RES
REV. 0