AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 39

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

REV. 0
NTSC
Divisor
1
2
3
4
5
6
7
8
*When C1M6:4 = “100,” base frequency is 48,000 Hz only if NTSC sync rate is increased by 1001/1000, or is exactly 15.750 kHz.
PAL
Divisor
1
2
3
4
5
6
7
8
C1C15:0
C1PD
C1P7:0
Address 17
Address 18
Data 15
Data 15
C1C15
Data 7
Data 7
C1C7
C1P7
res
Clock Generator 1 Conversion (Sample) Rate Select. Defines the conversion rate produced by Clock Generator 1
when not referenced to the SYNC1 pin (Control Register Address 16 Bit 15 [C1REF]). One LSB represents exactly
one Hertz, assuming a 24.576 MHz clock input on the XTALI pin. Usable range is 4 kHz (0x0FA0) to 54 kHz
(0xD2F0).
Initial default state after reset: 1011 1011 1000 0000 (BB80 hex), which is 48 kHz, assuming a 24.576 MHz clock in-
put on the XTALI pin. Cleared to default and cannot be written to when: the RESET pin is asserted LO; or when
the PWRDWN pin is asserted LO.
Clock Generator 1 Phase Shift Direction. This bit controls the direction of sample clock phase shift.
0 = Phase Advance
1 = Phase Retard
Clock Generator 1 Phase Shift Magnitude. These bits control the magnitude of sample clock phase shift. One LSB
represents exactly 0.12 degrees. LSBs are processed and decremented at a rate of 3.072 MHz (assuming a 24.576
MHz clock input on the XTALI pin). When this register is read, it indicates any phase advance/retard remaining to
be processed as of the beginning of slot 0 if bus master, or when TSI was received if bus slave. This register may be
(C1M7 = “0”):
(C1M3:0)
(0000)
(0001)
(0010)
(0011)
(0100)
(0101)
(0110)
(0111)
(C1M7 = “1”):
(C1M3:0)
(0000)
(0001)
(0010)
(0011)
(0100)
(0101)
(0110)
(0111)
Initial default state after reset: 0000 0000 1111 1111 (00FF hex). Cleared to default and cannot be written to
when: the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.
Data 14
Data 14
C1C14
Data 6
Data 6
C1C6
C1P6
res
Clock Generator 1 Control—Sample Rate
Clock Generator 1 Control—Sample Phase Shift
Data 13
Data 13
C1C13
Data 5
Data 5
C1C5
C1P5
res
Base Frequency In Hz (C1M6:4)
48,000
(000)
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Base Frequency In Hz (C1M6:4)
48,000
(000)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Data 12
Data 12
C1C12
Data 4
Data 4
C1C4
C1P4
res
32,000
(001)
Yes
Yes
No
Yes
Yes
No
No
No
32,000
(001)
Yes
Yes
No
Yes
Yes
No
No
No
–39–
Data 11
Data 11
C1C11
Data 3
Data 3
C1C3
C1P3
res
44,100
(010)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
44,100
(010)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Data 10
Data 10
C1C10
Data 2
Data 2
C1C2
C1P2
res
44,100
No
No
No
44,100
No
No
No
No
(011)
Yes
Yes
Yes
Yes
No
(011)
Yes
Yes
Yes
Yes
Data 9
Data 1
Data 9
Data 1
C1C1
C1C9
C1P1
2/3
2/3
res
48,000*
(100)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Data 8
Data 0
Data 8
Data 0
C1PD
C1C8
C1C0
C1P0
AD1843
44,056
(101)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes