AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 51

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

REV. 0
res
BIT AND REGISTER MAPS
A map of all TDM time slot bit assignments and Control Register contents is summarized for reference as follows in Figure 14
and Figure 15:
res
OUTPUT SLOT
INPUT SLOT
Address 30
Address 31
0 OR 16
1 OR 17
2 OR 18
3 OR 19
4 OR 20
5 OR 21
0 OR 16
1 OR 17
2 OR 18
3 OR 19
4 OR 20
5 OR 21
Data 15
Data 15
Data 7
Data 7
DATA 15
RES
DATA 15
DATA 15
DATA 15
RES
RES
DATA 15
RES
DATA 15
DATA 15
DATA 15
DATA 15
DATA 15
res
res
res
res
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.
DATA 14
RES
DATA 14
DATA 14
DATA 14
DATA 14
DATA 14
DATA 14
RES
DATA 14
DATA 14
DATA 14
RES
RES
Data 14
Data 14
Data 6
Data 6
DATA 13
RES
DATA 13
DATA 13
DATA 13
DATA 13
DATA 13
DATA 13
RES
DATA 13
DATA 13
DATA 13
RES
RES
res
res
res
res
DATA 12
RES
DATA 12
DATA 12
DATA 12
RES
RES
DATA 12
RES
DATA 12
DATA 12
DATA 12
DATA 12
DATA 12
Figure 14. AD1843 TDM Time Slot Bit Assignment Map
Reserved for Future Expansion
Reserved for Future Expansion
Data 13
Data 13
Data 5
Data 5
DATA 11
RES
DATA 11
DATA 11
DATA 11
DATA 11
DATA 11
DATA 11
RES
DATA 11
DATA 11
DATA 11
RES
RES
res
res
res
res
DATA 10
RES
DATA 10
DATA 10
DATA 10
RES
RES
DATA 10
RES
DATA 10
DATA 10
DATA 10
DATA 10
DATA 10
Data 12
Data 12
Data 4
Data 4
DATA 9
DA2V
DATA 9
DATA 9
DATA 9
DATA 9
DATA 9
DATA 9
ADRV
DATA 9
DATA 9
DATA 9
RES
RES
res
res
res
res
–51–
DATA 8
DA1V
DATA 8
DATA 8
DATA 8
DATA 8
DATA 8
DATA 8
ADLV
DATA 8
DATA 8
DATA 8
RES
RES
Data 11
Data 11
Data 3
Data 3
DATA 7
RES
DATA 7
DATA 7
DATA 7
RES
RES
DATA 7
R/W
DATA 7
DATA 7
DATA 7
DATA 7
DATA 7
res
res
res
res
DATA 6
RES
DATA 6
DATA 6
DATA 6
RES
RES
DATA 6
RES
DATA 6
DATA 6
DATA 6
DATA 6
DATA 6
Data 10
Data 10
Data 2
Data 2
DATA 5
RES
DATA 5
DATA 5
DATA 5
RES
RES
res
res
DATA 5
RES
DATA 5
DATA 5
DATA 5
DATA 5
DATA 5
res
res
DATA 4
RES
DATA 4
DATA 4
DATA 4
RES
RES
DATA 4
IA4
DATA 4
DATA 4
DATA 4
DATA 4
DATA 4
Data 9
Data 1
Data 9
Data 1
res
res
DATA 3
RES
DATA 3
DATA 3
DATA 3
RES
RES
res
res
DATA 3
IA3
DATA 3
DATA 3
DATA 3
DATA 3
DATA 3
DATA 2
RES
DATA 2
DATA 2
DATA 2
RES
RES
DATA 2
IA2
DATA 2
DATA 2
DATA 2
DATA 2
DATA 2
Data 8
Data 0
Data 8
Data 0
res
res
AD1843
DATA 1
DA2RQ
DATA 1
DATA 1
DATA 1
RES
RES
res
res
DATA 1
IA1
DATA 1
DATA 1
DATA 1
DATA 1
DATA 1
DATA 0
DA1RQ
DATA 0
DATA 0
DATA 0
RES
RES
DATA 0
IA0
DATA 0
DATA 0
DATA 0
DATA 0
DATA 0