APA600-CQ208B

Manufacturer Part NumberAPA600-CQ208B
DescriptionFPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
ManufacturerActel
APA600-CQ208B datasheet
 


Specifications of APA600-CQ208B

Package208CQFPFamily NameProASICPLUS
Device System Gates600000Number Of Registers21504
Maximum Internal Frequency180 MHzTypical Operating Supply Voltage2.5 V
Maximum Number Of User I/os158Ram Bits129024
Re-programmability SupportYes  
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PLUS®
ProASIC
Flash Family FPGAs
Features and Benefits
High Capacity
Commercial and Industrial
75,000 to 1 Million System Gates
27 K to 198 Kbits of Two-Port SRAM
66 to 712 User I/Os
Military
300, 000 to 1 Million System Gates
72 K to 198 Kbits of Two Port SRAM
158 to 712 User I/Os
Reprogrammable Flash Technology
0.22 µm 4 LM Flash-Based CMOS Process
Live At Power-Up (LAPU) Level 0 Support
Single-Chip Solution
No Configuration Device Required
Retains Programmed Design during Power-Down/Up Cycles
Mil/Aero Devices Operate over Full Military Temperature
Range
Performance
3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military
temperature)
Two Integrated PLLs
External System Performance up to 150 MHz
Secure Programming
The Industry’s Most Effective Security Key (FlashLock
Low Power
Low Impedance Flash Switches
Segmented Hierarchical Routing Structure
Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
PLUS
Table 1 • ProASIC
Product Profile
Device
Maximum System Gates
Tiles (Registers)
Embedded RAM Bits (k=1,024 bits)
Embedded RAM Blocks (256x9)
LVPECL
PLL
Global Networks
Maximum Clocks
Maximum User I/Os
JTAG ISP
PCI
Package (by pin count)
TQFP
PQFP
PBGA
FBGA
2
CQFP
2
CCGA/LGA
Notes:
1. Available as Commercial/Industrial and Military/MIL-STD-883B devices.
2. These packages are available only for Military/MIL-STD-883B devices.
D e c e m b er 2 0 0 9
© 2009 Actel Corporation
High Performance Routing Hierarchy
Ultra-Fast Local and Long-Line Network
High-Speed Very Long-Line Network
High-Performance, Low Skew, Splittable Global Network
100% Routability and Utilization
I/O
Schmitt-Trigger Option on Every Input
2.5 V / 3.3 V Support with Individually-Selectable Voltage
and Slew Rate
Bidirectional Global I/Os
Compliance with PCI Specification Revision 2.2
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
Pin-Compatible Packages across the ProASIC
Unique Clock Conditioning Circuitry
PLL with Flexible Phase, Multiply/Divide, and Delay
Capabilities
Internal and/or External Dynamic PLL Configuration
Two LVPECL Differential Pairs for Clock or Data Inputs
Standard FPGA and ASIC Design Flow
Flexibility with Choice of Industry-Standard Front-End Tools
Efficient Design through Front-End Timing and Gate
Optimization
ISP Support
In-System Programming (ISP) via JTAG Port
SRAMs and FIFOs
SmartGen Netlist Generation Ensures Optimal Usage of
®
)
Embedded Memory Blocks
24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
1
APA075
APA150
APA300
75,000
150,000
300,000
3,072
6,144
8,192
27 k
36k
72 k
12
16
32
2
2
2
2
2
2
4
4
4
24
32
32
158
242
290
Yes
Yes
Yes
Yes
Yes
Yes
100, 144
100
208
208
208
456
456
144
144, 256
144, 256
144, 256, 484
208, 352
PLUS
1
APA450
APA600
APA750
450,000
600,000
750,000
12,288
21,504
32,768
108 k
126 k
144 k
48
56
64
2
2
2
2
2
2
4
4
4
48
56
64
344
454
562
Yes
Yes
Yes
Yes
Yes
Yes
208
208
208
456
456
456
256, 484, 676
676, 896
208, 352
624
See the Actel website for the latest version of the datasheet.
v5.9
v5.9
®
Family
1
APA1000
1,000,000
56,320
198 k
88
2
2
4
88
712
Yes
Yes
208
456
896, 1152
208, 352
624
i

APA600-CQ208B Summary of contents

  • Page 1

    ... Yes Yes Yes Yes Yes Yes 100, 144 100 – 208 208 208 – 456 456 144 144, 256 144, 256 144, 256, 484 208, 352 PLUS 1 APA450 APA600 APA750 450,000 600,000 750,000 12,288 21,504 32,768 108 k 126 k 144 ...

  • Page 2

    ... Blank = Standard Speed Part Number APA075 = 75,000 Equivalent System Gates APA150 = 150,000 Equivalent System Gates APA300 = 300,000 Equivalent System Gates APA450 = 450,000 Equivalent System Gates APA600 = 600,000 Equivalent System Gates APA750 = 750,000 Equivalent System Gates APA1000 = 1,000,000 Equivalent System Gates ii G 1152 ...

  • Page 3

    ... APA150 66 158 5 APA300 158 APA450 158 5 APA600 158 APA750 158 5 APA1000 158 Notes: 1. Package Definitions: TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array, CQFP = Ceramic Quad Flat Pack, CCGA = Ceramic Column Grid Array, LGA = Land Grid Array 2. Each pair of PECL I/Os is counted as one user I/O. 3. Available in RoHS compatible packages. Ordering code is " ...

  • Page 4

    ... Package TQ100 TQ144 PQ208 BG456 FG144 FG256 FG484 FG676 FG896 FG1152 CQ208 CQ352 CG624 Note Commercial I = Industrial M = Military B = MIL-STD-883 Speed Grade and Temperature Matrix Note Commercial I = Industrial M = Military B = MIL-STD-883 iv APA075 APA150 APA300 v5.9 APA450 APA600 APA750 Std. ✓ ✓ ✓ APA1000 ...

  • Page 5

    ... PLUS The ProASIC family of devices, Actel’s second- generation family of flash FPGAs, offers enhanced performance over Actel’s ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile flash technology. This enables engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, ...

  • Page 6

    PLUS ProASIC Flash Family FPGAs PLUS ProASIC Architecture PLUS The proprietary ProASIC architecture granularity comparable to gate arrays. PLUS The ProASIC device core consists of a Sea-of-Tiles (Figure 1-1). Each tile can be configured as a three-input logic function (e.g., ...

  • Page 7

    ... (CLK (Reset) Figure 1-3 • Core Logic Tile Live at Power-Up PLUS The Actel flash-based ProASIC Level 0 of the live at power-up (LAPU) classification standard. This feature helps in system component initialization, executing critical processor wakes up, setting up and configuring memory blocks, clock generation, and bus activity management. ...

  • Page 8

    ... The Actel products described in this advance status datasheet may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life- support, and other high-reliability applications. Consult Actel’ ...

  • Page 9

    ... FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51 896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59 1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69 624-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Export Administration Regulations (EAR 4-8 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . 2-51 v5.9 PLUS ...

  • Page 10

    ...

  • Page 11

    General Description Routing Resources PLUS The routing structure of ProASIC to provide high performance through a flexible four- level hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high-speed, very long-line resources, and high performance global networks. The ultra-fast ...

  • Page 12

    PLUS ProASIC Flash Family FPGAs Spans 4 Tiles Figure 2-2 • Efficient Long-Line Resources 2 -2 Spans 2 Tiles Spans 1 Tile ...

  • Page 13

    ... Users can also drastically reduce delay penalties and save buffering resources by mapping critical high fanout nets to spines. For design hints on using these features, refer to Actel’s ProASIC Clock Trees v5.9 PLUS ...

  • Page 14

    ... APA150 APA300 512 768 1,024 3,072 6,144 8,192 v5.9 High-Performance Global Network Global Networks Global Pads Global Spine Global Ribs Scope of Spine (Shaded area plus local RAMs and I/Os) APA450 APA600 APA750 APA1000 1,024 1,536 2,048 12,288 21,504 32,768 2,560 56,320 ...

  • Page 15

    ... Array Coordinates Logic Tile Min. Device x y APA075 1 1 APA150 1 1 APA300 1 5 APA450 1 5 APA600 1 5 APA750 1 5 APA1000 1 5 (1,169) (1,167) (1,165) (1,164) (1,5) (1,3) (1,1) (0,0) Figure 2-5 • Core Cell Coordinates for the APA1000 cells and core cells. In addition, the I/O coordinate system changes depending on the die/package combination ...

  • Page 16

    PLUS ProASIC Flash Family FPGAs Input/Output Blocks To meet complex system demands, the ProASIC family offers devices with a large number of user I/O pins 712 on the APA1000. available supply voltage configurations (the PLL block uses an ...

  • Page 17

    ... DD PLUS V on ProASIC devices. Failure to follow these DDP guidelines may result in undesirable pin behavior during system start-up. For more information, refer to Actel’s PLUS Power-Up Behavior of ProASIC note. LVPECL Input Pads In addition to standard I/O pads and power pads, PLUS ProASIC ...

  • Page 18

    ... Boundary-Scan Opcodes EXTEST SAMPLE/PRELOAD IDCODE 2 -8 pins are dedicated for boundary-scan test usage. Actel recommends that a nominal 20 kΩ pull-up resistor is added to TDO and TCK pins. The TAP controller is a four-bit state machine (16 states) that operates as shown in 1s and 0s represent the values that must be present at TMS at a rising edge of TCK for the given state transition 2-9) ...

  • Page 19

    The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller ...

  • Page 20

    PLUS ProASIC Flash Family FPGAs Timing Control and Characteristics PLUS ProASIC Clock Management System PLUS ProASIC devices provide designers with very flexible clock conditioning capabilities. Each member of the PLUS ProASIC family contains two phase-locked loop (PLL) blocks which perform ...

  • Page 21

    The clock conditioning circuit can advance or delay the clock (in increments of 0.25 ns) relative to the positive edge of the incoming reference clock. The system also allows for the selection of output frequency clock ...

  • Page 22

    PLUS ProASIC Flash Family FPGAs Package Pins Physical I/O Buffers GL Std. Pad Cell NPECL PECL Pad Cell PPECL GLMX Std. Pad Cell GL Std. Pad Cell Legend Physical Pin DATA Signals to the Core DATA Signals to the PLL ...

  • Page 23

    ... The shift register can be accessed either from user logic within the device or via the JTAG port. Another option is internal dynamic configuration hardware. Refer to Actel's ProASIC Reconfiguration Using JTAG application note for more information. For information on the clock conditioning circuit, refer PLUS to Actel’ ...

  • Page 24

    PLUS ProASIC Flash Family FPGAs Global MUX B OUT 33 MHz External Feedback Global MUX A OUT Figure 2-13 • Using the PLL 33 MHz In, 133 MHz Out Global MUX B OUT 40 MHz External Feedback Global MUX A ...

  • Page 25

    Global MUX B OUT 133 MHz External Feedback Global MUX A OUT Figure 2-15 • Using the PLL to Delay the Input Clock Global MUX B OUT 133 MHz External Feedback Global MUX A OUT Figure 2-16 • Using the ...

  • Page 26

    PLUS ProASIC Flash Family FPGAs On-Chip Off-Chip Global MUX B OUT 133 MHz External Feedback Global MUX A OUT Reference Clock Figure 2-17 • Using the PLL for Clock Deskewing 180° ÷n PLL Core 0° ÷m ...

  • Page 27

    ... The derating factors shown in should be applied to all timing data contained within this datasheet. All timing numbers listed in this datasheet represent sample timing characteristics of ProASIC Actual timing delay values are design-specific and can be derived from the Timer tool in Actel’s Designer software after place-and-route. = 70° 2 0° ...

  • Page 28

    PLUS ProASIC Flash Family FPGAs PLL Electrical Specifications Parameter Frequency Ranges Reference Frequency f (min.) IN Reference Frequency f (max.) IN OSC Frequency f (min.) VCO OSC Frequency f (max.) VCO Clock Conditioning Circuitry f (min.) OUT Clock Conditioning Circuitry ...

  • Page 29

    ... PLL locking is guaranteed only when using low drive strength and low slew rate I/O. PLL locking may be inconsistent when using high drive strength or high slew rate I/Os SSO APA300 APA600 APA1000 APA300 APA600 APA1000 ProASIC ≤ T –40°C J ≤ Hermetic packages 8 SSO ≤ ...

  • Page 30

    ... PLUS Table 2-12 • ProASIC Memory Configurations by Device Device Bottom APA075 0 APA150 0 APA300 16 APA450 24 APA600 28 APA750 32 APA1000 Embedded Memory Configurations The embedded memory in the ProASIC provides great configuration flexibility PLUS Table 2-11 ProASIC port memory (one read, one write). This provides 198 kbits of two-port and/or single port memory in the APA1000 device ...

  • Page 31

    Table 2-13 • Basic Memory Configurations Type Write Access RAM Asynchronous RAM Asynchronous RAM Asynchronous RAM Asynchronous RAM Asynchronous RAM Asynchronous RAM Synchronous RAM Synchronous RAM Synchronous RAM Synchronous RAM Synchronous RAM Synchronous FIFO Asynchronous FIFO Asynchronous FIFO Asynchronous FIFO ...

  • Page 32

    PLUS ProASIC Flash Family FPGAs DI <0:8> SRAM WADDR <0:7> (256x9) WRB WBLKB Sync Write WCLKS and Sync Read Ports WPE PARODD DI <0:8> SRAM WADDR <0:7> (256x9) WRB WBLKB Sync Write and WCLKS Async Read Ports WPE PARODD Note: ...

  • Page 33

    DI<0:8> LEVEL<0:7> LGDEP<0:2> FIFO (256x9) WRB WBLKB Sync Write RDB and Sync Read RBLKB Ports PARODD WCLKS DI <0:8> LEVEL <0:7> FIFO LGDEP<0:2> (256x9) WRB WBLKB Async Write RDB and Sync Read RBLKB Ports PARODD Note: Each RAM block contains ...

  • Page 34

    PLUS ProASIC Flash Family FPGAs Word Depth Figure 2-20 • APA1000 Memory Block Architecture Word Width Word 256 Depth 256 256 256 1,024 words x 9 bits, 1 read, 1 write Figure 2-21 • Example Showing Memory Arrays with Different ...

  • Page 35

    ... Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see Actel’s website for more information about ® IDE includes Synplify AE from Synplicity® ...

  • Page 36

    ... PLUS Using ProASIC Clock Conditioning Circuits http://www.actel.com/documents/APA_PLL_AN.pdf PLUS In-System Programming ProASIC http://www.actel.com/documents/APA_External_ISP_AN.pdf Performing Internal In-System Programming Using Actel’s ProASIC http://www.actel.com/documents/APA_Microprocessor_AN.pdf PLUS ProASIC RAM and FIFO Blocks http://www.actel.com/documents/APA_RAM_FIFO_AN.pdf White Paper Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.actel.com/documents/DesignSecurity_WP.pdf User’ ...

  • Page 37

    ... Ceramic Column Grid Array (CCGA/LGA) Notes: 1. Valid for the following devices irrespective of temperature grade: APA075, APA150, and APA300 2. Valid for the following devices irrespective of temperature grade: APA450, APA600, APA750, and APA1000 3. Depopulated array 4. Full array surface of the integrated circuit (IC) and is 110° defined as shown in Θ ...

  • Page 38

    ... total dc ac where for the APA075 for the APA150 11 mW for the APA300 12 mW for the APA450 12 mW for the APA600 13 mW for the APA750 19 mW for the APA1000 P includes the static components clock storage logic Global Clock Contribution—P ...

  • Page 39

    Logic-Tile Contribution—P logic P , the logic-tile component of AC power dissipation, is given by logic logic where: 1.4 μW/MHz is the average power consumption of a logic tile per MHz of its ...

  • Page 40

    PLUS ProASIC Flash Family FPGAs The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. ...

  • Page 41

    ... No forced ventilation cooling system is in use years after APA600-PQ208M dissipating Table 2-19 on (junction-to-ambient) in still air that the junction temperature of the FPGA will be 120°C (25% of the time) and 70°C (75% of the time). The entry ...

  • Page 42

    PLUS ProASIC Flash Family FPGAs Table 2-19 • Military Temperature Grade Product Performance Retention Minimum Time at T Minimum Time 110°C or Below 125°C or Below 100% 90% 10% 75% 25% 90% 50% 50% 90% 75% 100% ...

  • Page 43

    Table 2-20 • Recommended Maximum Operating Conditions Programming and PLL Supplies Parameter Condition V During Programming PP Normal Operation V During Programming PN Normal Operation I During Programming PP I During Programming PN AVDD AGND Notes: 1. Please refer to ...

  • Page 44

    PLUS ProASIC Flash Family FPGAs Table 2-22 • DC Electrical Specifications (V Symbol Parameter V Output High Voltage OH High Drive (OB25LPH) Low Drive (OB25LPL) V Output Low Voltage OL High Drive (OB25LPH) Low Drive (OB25LPL Input High ...

  • Page 45

    Table 2-22 • DC Electrical Specifications (V Symbol Parameter I Output Short Circuit Current Low OSL High Drive (OB25LPH) Low Drive (OB25LPL) C I/O Pad Capacitance I/O C Clock Input Pad Capacitance CLK Notes: 1. All process conditions. Commercial/Industrial: Junction ...

  • Page 46

    PLUS ProASIC Flash Family FPGAs Table 2-23 • DC Electrical Specifications (V Applies to Commercial and Industrial Temperature Only Symbol Parameter V Output High Voltage OH 3.3 V I/O, High Drive (OB33P) 3.3 V I/O, Low Drive (OB33L) V Output ...

  • Page 47

    Table 2-23 • DC Electrical Specifications (V Applies to Commercial and Industrial Temperature Only Symbol Parameter I Output Short Circuit Current OSH High 3.3 V High Drive (OB33P) 3.3 V Low Drive (OB33L) I Output Short Circuit Current OSL Low ...

  • Page 48

    PLUS ProASIC Flash Family FPGAs Table 2-24 • DC Electrical Specifications (V Applies to Military Temperature and MIL-STD-883B Temperature Only Symbol Parameter V Output High Voltage OH 3.3 V I/O, High Drive, High Slew (OB33PH) 3.3V I/O, High Drive, Normal/ ...

  • Page 49

    Table 2-24 • DC Electrical Specifications (V Applies to Military Temperature and MIL-STD-883B Temperature Only Symbol Parameter I Quiescent Supply Current DDQ (standby) Military I Tristate Output Leakage OZ Current I Output Short Circuit Current OSH High 3.3 V High ...

  • Page 50

    PLUS ProASIC Flash Family FPGAs Table 2-25 • DC Specifications (3.3 V PCI Operation) Symbol Parameter V Supply Voltage for Core DD V Supply Voltage for I/O Ring DDP V Input High Voltage IH V Input Low Voltage IL 3 ...

  • Page 51

    Table 2-26 • AC Specifications (3.3 V PCI Revision 2.2 Operation) Symbol Parameter Condition I Switching Current High 0 < V OH(AC) 0.3V 0.7V (Test Point) V OUT I Switching Current Low V OL(AC) DDP 0.6V 0.18V (Test Point) V ...

  • Page 52

    PLUS ProASIC Flash Family FPGAs Tristate Buffer Delays A 50% 50 PAD 50 DLH DHL Figure 2-23 • Tristate Buffer Delays Table 2-27 • Worst-Case Commercial Conditions 2.3 ...

  • Page 53

    Table 2-29 • Worst-Case Military Conditions load, T DDP DD Macro Type Description OTB33PH 3.3 V, PCI Output Current, High Slew Rate OTB33PN 3.3 V, High Output Current, Nominal Slew ...

  • Page 54

    PLUS ProASIC Flash Family FPGAs Output Buffer Delays A Figure 2-24 • Output Buffer Delays Table 2-31 • Worst-Case Commercial Conditions load, T DDP DD Macro Type OB33PH 3.3 V, ...

  • Page 55

    Table 2-33 • Worst-Case Military Conditions V = 3.0V 2.3V load, T DDP DD Macro Type Description OB33PL 3.3V, High Output Current, Low Slew Rate OB33LH 3.3V, Low Output Current, High Slew Rate OB33LN 3.3V, Low ...

  • Page 56

    PLUS ProASIC Flash Family FPGAs Input Buffer Delays PAD Figure 2-25 • Input Buffer Delays Table 2-35 • Worst-Case Commercial Conditions DDP DD Macro Type IB33 3.3 V, CMOS Input Levels ...

  • Page 57

    Table 2-37 • Worst-Case Military Conditions V = 3.0V 2.3V, T DDP DD Macro Type Description IB33 3.3 V, CMOS Input Levels IB33S 3.3 V, CMOS Input Levels Notes Input Pad-to-Y High INYH 2. t ...

  • Page 58

    PLUS ProASIC Flash Family FPGAs Global Input Buffer Delays Table 2-39 • Worst-Case Commercial Conditions DDP DD Macro Type GL33 3.3 V, CMOS Input Levels GL33S 3.3 V, CMOS Input Levels ...

  • Page 59

    Table 2-41 • Worst-Case Military Conditions V = 3.0V 2.3V, T DDP DD Macro Type GL33 3.3V, CMOS Input Levels GL33S 3.3V, CMOS Input Levels PECL PPECL Input Levels Notes Input Pad-to-Y High INYH 2. ...

  • Page 60

    PLUS ProASIC Flash Family FPGAs Predicted Global Routing Delay Table 2-43 • Worst-Case Commercial Conditions DDP DD Parameter t Input Low to High RCKH t Input High to Low RCKL t ...

  • Page 61

    Module Delays Figure 2-26 • Module Delays Sample Macrocell Library Listing Table 2-47 • Worst-Case Military Conditions 70º Cell Name NAND2 2-Input NAND AND2 2-Input AND ...

  • Page 62

    PLUS ProASIC Flash Family FPGAs Table 2-48 • Recommended Operating Conditions Parameter Maximum Clock Frequency* Maximum RAM Frequency* Maximum Rise/Fall Time on Inputs* • Schmitt Trigger Mode (10% to 90%) • Non-Schmitt Trigger Mode (10% to 90%) Maximum LVPECL Frequency* ...

  • Page 63

    Table 2-50 • JTAG Switching Characteristics Description Output delay from TCK falling to TDI, TMS TDO Setup time before TCK rising TDO Hold time after TCK rising TCK period RCK period Notes: 1. For DC electrical specifications of the JTAG ...

  • Page 64

    PLUS ProASIC Flash Family FPGAs Embedded Memory Specifications PLUS This section discusses ProASIC SRAM/FIFO embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks Table 2-13 on ...

  • Page 65

    Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) RCLKS RBD, RBLKB RADDR Note: The plot shows the normal operation status. Figure 2-28 • Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) Table 2-52 • 0°C to ...

  • Page 66

    PLUS ProASIC Flash Family FPGAs Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLKS RDB, RBLKB New Valid RADDR Address DO RPE t RACS t RACH t RDCH t RDCS Note: The plot shows the normal operation status. Figure 2-29 ...

  • Page 67

    Asynchronous SRAM Write WADDR WRB, WBLKB DI WPE t AWRS t WPDA Note: The plot shows the normal operation status. Figure 2-30 • Asynchronous SRAM Write Table 2-54 • 0°C to 110° 2 2.7 ...

  • Page 68

    PLUS ProASIC Flash Family FPGAs Asynchronous SRAM Read, Address Controlled, RDB=0 RADDR DO RPE Note: The plot shows the normal operation status. Figure 2-31 • Asynchronous SRAM Read, Address Controlled, RDB = 0 Table 2-55 • 0°C to ...

  • Page 69

    Table 2-56 • 0°C to 110° 2 2.7 V for Commercial/Industrial –55°C to 150° Symbol t Description xxx New DO access from RB ↓ ORDA Old DO ...

  • Page 70

    PLUS ProASIC Flash Family FPGAs Synchronous SRAM Write WCLKS WRB, WBLKB WADDR, DI WPE t WRCH , t WBCH t WRCS , t WBCS t DCS , t WDCS t WPCH t DCH , t WACH Note: The plot shows ...

  • Page 71

    Synchronous Write and Read to the Same Location RCLKS DO Last Cycle Data WCLKS t WCLKRCLKH t WCLKRCLKS t OCH t OCA ↑ Note: * New data is read if WCLKS occurs before setup time. The data stored is read ...

  • Page 72

    PLUS ProASIC Flash Family FPGAs Asynchronous Write and Synchronous Read to the Same Location RCLKS Last Cycle Data {WRB + WBLKB WRCKS t BRCLKH t OCH t OCA t DWRRCLK ↓ Note: *New data is ...

  • Page 73

    Asynchronous Write and Read to the Same Location RB, RADDR {WRB+WBLKB} t ORDA t ORDH t RAWRS Note: The plot shows the normal operation status. Figure 2-36 • Asynchronous Write and Read to the Same Location Table ...

  • Page 74

    PLUS ProASIC Flash Family FPGAs Synchronous Write and Asynchronous Read to the Same Location RB, RADDR DO WCLKS t ORDA t ORDH t RAWCLKS Note: The plot shows the normal operation status. Figure 2-37 • Synchronous Write and Asynchronous Read ...

  • Page 75

    Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem ...

  • Page 76

    PLUS ProASIC Flash Family FPGAs FULL RB Write Write Inhibited Cycle WB Figure 2-38 • Write Timing Diagram EMPTY WB Read Read Inhibited Cycle RB Figure 2-39 • Read Timing Diagram ...

  • Page 77

    Asynchronous FIFO Read RB = (RDB+RBLKB) RDATA EMPTY EQTH, GETH t RDWRS Note: The plot shows the normal operation status. Figure 2-40 • Asynchronous FIFO Read Table 2-63 • 0°C to 110° 2 2.7 ...

  • Page 78

    PLUS ProASIC Flash Family FPGAs Asynchronous FIFO Write WB = (WRB + WBLKB) EQTH, GETH Note: The plot shows the normal operation status. Figure 2-41 • Asynchronous FIFO Write Table 2-64 • 0°C to 110° 2.3 ...

  • Page 79

    Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) RCLK RDB RDATA RPE EMPTY FULL EQTH, GETH Note: The plot shows the normal operation status. Figure 2-42 • Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) Table 2-65 • ...

  • Page 80

    PLUS ProASIC Flash Family FPGAs Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLK RDB RDATA RPE EMPTY FULL EQTH, GETH Note: The plot shows the normal operation status. Figure 2-43 • Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) ...

  • Page 81

    Synchronous FIFO Write WCLKS WRB, WBLKB WPE FULL EMPTY EQTH, GETH t WRCH , t WBCH t WRCS , t WBCS Note: The plot shows the normal operation status. Figure 2-44 • Synchronous FIFO Write Table 2-67 • ...

  • Page 82

    PLUS ProASIC Flash Family FPGAs FIFO Reset RESETB WRB/RBD WCLKS, RCLKS FULL EMPTY EQTH, GETH t ERSA , t FRSA t THRSA Notes: 1. During reset, either the enables (WRB and RBD) OR the clocks (WCLKS and RCKLS) must be ...

  • Page 83

    ... DDP 2 3.3 V supply voltage. TMS The TMS pin controls the use of boundary-scan circuitry. This pin has an internal pull-up resistor. TCK Clock input pin for boundary scan (maximum 10 MHz). Actel recommends adding a nominal 20 kΩ pull-up resistor to this pin. and LVCMOS TDI Serial input for boundary scan ...

  • Page 84

    ... Actel recommends floating the pin or connecting it to GND. Recommended Design Practice for PLUS ProASIC Devices – APA450, APA600, APA750, APA1000 Bypass capacitors are required from V PLUS to GND for all ProASIC devices during programming. PLUS During the erase cycle, ProASIC current surges on the V ...

  • Page 85

    ... Package Pin Assignments 100-Pin TQFP 100 1 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC 100-Pin TQFP v5.9 PLUS Flash Family FPGAs 3-1 ...

  • Page 86

    PLUS ProASIC Flash Family FPGAs 100-Pin TQFP Pin APA075 APA150 Number Function Function 1 GND GND 2 I/O I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 GND GND ...

  • Page 87

    ... TQFP 144 1 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC 144-Pin TQFP v5.9 PLUS Flash Family FPGAs 3-3 ...

  • Page 88

    PLUS ProASIC Flash Family FPGAs 144-Pin TQFP Pin APA075 Number Function Number 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I GND 11 V DDP 12 I/O 13 I/O ...

  • Page 89

    ... PQFP 208 1 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC 208-Pin PQFP v5.9 PLUS Flash Family FPGAs 3-5 ...

  • Page 90

    ... GND I/O / GL1 I/O / GL1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v5.9 APA600 APA750 APA1000 Function Function Function GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 91

    ... I/O I/O 63 I/O I/O 64 I/O I/O 65 GND GND 66 I/O I/O 67 I/O I/O 68 I/O I/O 69 I/O I/O 70 I/O I/O 208-Pin PQFP APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I DDP DDP DDP GND GND GND I/O ...

  • Page 92

    ... I/O I/O I/O I/O I/O I/O I/O I/O TCK TCK TCK TDI TDI TDI TMS TMS TMS V V DDP DDP DDP GND GND v5.9 APA600 APA750 APA1000 Function Function Function DDP DDP DDP I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 93

    ... I/O / GL4 I/O / GL4 135 I/O / GLMX2 I/O / GLMX2 136 I/O I/O 137 I/O I/O 138 V V DDP DDP 139 I/O I/O 140 I/O I/O 208-Pin PQFP APA300 APA450 APA600 Function Function Function TDO TDO TDO TRST TRST TRST RCK RCK RCK ...

  • Page 94

    ... I/O I/O I/O I DDP DDP DDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v5.9 APA600 APA750 APA1000 Function Function Function GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 95

    ... I/O I/O 205 I/O I/O 206 I/O I/O 207 I/O I/O 208 V V DDP DDP 208-Pin PQFP APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 96

    ... Flash Family FPGAs 208-Pin CQFP No Ceramic Tie Bar Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx 208-Pin CQFP v5.9 156 155 154 153 142 141 140 139 138 137 136 135 134 108 107 106 105 ...

  • Page 97

    ... I/O / GL2 59 AGND 60 NPECL1 61 AVDD 62 63 GND 64 I/O / GL1 65 I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 v5.9 PLUS ProASIC Flash Family FPGAs 208-Pin CQFP APA600 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I DDP DDP DDP GND GND GND I/O ...

  • Page 98

    ... I/O 130 I/O 131 GND 132 I/O 133 I/O 134 I/O 135 TCK 136 TDI 137 TMS 138 V 139 DDP GND 140 v5.9 208-Pin CQFP APA300 APA600 APA1000 Function Function Function TDO TDO TDO TRST TRST TRST RCK RCK RCK I/O ...

  • Page 99

    ... I/O 204 V 205 DDP V 206 DD I/O 207 I/O 208 I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 208-Pin CQFP APA600 APA1000 Function Function I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 100

    ... Flash Family FPGAs 352-Pin CQFP Pin Ceramic Tie Bar Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx 352-Pin CQFP v5.9 264 263 262 261 223 222 221 220 219 218 217 216 215 180 179 178 177 ...

  • Page 101

    ... DDP I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 v5.9 PLUS ProASIC Flash Family FPGAs 352-Pin CQFP APA600 APA1000 Function Function I/O / GLMX1 I/O / GLMX1 I/O / GL2 I/O / GL2 AGND AGND AVDD AVDD NPECL1 NPECL1 I/O / GL1 I/O / GL1 I/O I/O I/O I/O ...

  • Page 102

    ... DD DD I/O 140 I/O 141 I/O 142 I/O 143 I/O 144 I/O 145 I/O 146 I/O 147 V 148 DDP v5.9 352-Pin CQFP APA300 APA600 APA1000 Function Function Function GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 103

    ... I/O 219 V 220 DDP GND 221 I/O / GL3 V 222 PPECL2 / Input PPECL2 / Input PPECL2 / Input DD v5.9 PLUS ProASIC Flash Family FPGAs 352-Pin CQFP APA600 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 104

    ... I/O 290 I/O 291 I/O 292 V 293 DDP GND 294 V 295 DD DD I/O 296 v5.9 352-Pin CQFP APA300 APA600 APA1000 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 105

    ... DD GND V DDP I/O I/O I/O I/O I/O I/O I/O I GND V DDP I/O I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 352-Pin CQFP APA600 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I GND ...

  • Page 106

    ... PLUS ProASIC Flash Family FPGAs 456-Pin PBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx v5.9 A1 Ball Pad Corner ...

  • Page 107

    ... NC A21 NC A22 NC A23 NC A24 NC A25 V DDP A26 V DDP B1 V DDP B2 V DDP I/O 456-Pin PBGA APA450 APA600 Function Function DDP DDP DDP DDP NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 108

    ... I/O C9 I/O C10 I/O C11 I/O C12 I/O C13 I/O C14 I/O C15 I/O C16 I 456-Pin PBGA APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 109

    ... D15 I/O D16 I/O D17 I/O D18 I/O D19 I/O D20 I/O D21 I/O D22 NC D23 V DDP D24 NC 456-Pin PBGA APA450 APA600 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O NC I/O I/O NC I/O ...

  • Page 110

    ... E17 I/O E18 I/O E19 I/O E20 V DD E21 V DD E22 V DD E23 NC E24 NC E25 NC E26 F22 456-Pin PBGA APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 111

    ... J1 I/O J2 I/O J3 I/O J4 I/O J5 I/O J22 I/O J23 I/O J24 I/O J25 I/O J26 I/O 456-Pin PBGA APA450 APA600 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 112

    ... L26 I/O M1 I/O / GL1 M2 I/O / GL2 M3 I/O M4 I/O M5 I/O M11 GND M12 GND M13 GND 456-Pin PBGA APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 113

    ... I/O P3 I/O P4 I/O P5 NPECL1 NPECL1 P11 GND P12 GND P13 GND P14 GND P15 GND 456-Pin PBGA APA450 APA600 Function Function GND GND GND GND GND GND GND GND GND I/O / GL4 I/O / GL4 I/O I/O I/O I/O I/O I/O I/O ...

  • Page 114

    ... I/O I/O I/O I/O GND GND GND GND GND GND GND GND GND GND GND GND I/O I/O v5.9 APA600 APA750 APA1000 Function Function Function GND GND I/O I/O I/O I/O I/O I/O I/O I/O PPECL2 / Input PPECL2 / Input I/O I/O ...

  • Page 115

    ... I/O W2 I/O W3 I W22 V DD W23 I/O W24 I/O W25 I/O W26 I/O 456-Pin PBGA APA450 APA600 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 116

    ... AB5 V DD AB6 V DD AB7 V DD AB8 I/O AB9 I/O AB10 I/O AB11 I/O AB12 I/O AB13 I/O AB14 I 456-Pin PBGA APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O ...

  • Page 117

    ... I/O AC13 I/O AC14 I/O AC15 I/O AC16 I/O AC17 I/O AC18 I/O AC19 I/O AC20 I/O AC21 TMS AC22 TDO 456-Pin PBGA APA450 APA600 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I ...

  • Page 118

    ... I/O AD20 NC AD21 TCK AD22 V PP AD23 NC AD24 V DDP AD25 NC AD26 NC AE1 V DDP AE2 V DDP AE3 NC AE4 456-Pin PBGA APA300 APA450 APA600 Function Function Function V V DDP DDP RCK RCK NC I/O I/O I I/O I DDP DDP NC I/O NC I/O NC I/O I/O I/O I/O ...

  • Page 119

    ... AF2 V DDP AF3 NC AF4 NC AF5 NC AF6 NC AF7 NC AF8 NC AF9 I/O AF10 I/O AF11 I/O AF12 I/O 456-Pin PBGA APA450 APA600 Function Function NC I/O I/O NC I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 120

    ... I/O AF17 I/O AF18 NC AF19 NC AF20 NC AF21 NC AF22 NC AF23 TDI AF24 NC AF25 V DDP AF26 V DDP 456-Pin PBGA APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC I/O NC I/O NC I/O NC I/O TDI TDI NC I/O ...

  • Page 121

    ... FBGA 12 11 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.9 PLUS ProASIC Flash Family FPGAs 3-37 ...

  • Page 122

    PLUS ProASIC Flash Family FPGAs 144-FBGA Pin Pin APA075 APA150 Number Function Function Function A1 I/O I/O A2 I/O I/O A3 I/O I/O A4 I/O I/O A5 I/O I/O A6 GND GND A7 I/O I ...

  • Page 123

    Pin Pin APA075 APA150 Number Function Function Function G1 PPECL1 / PPECL1 / Input Input G2 GND GND G3 AVDD AVDD G4 NPECL1 NPECL1 G5 GND GND G6 GND GND G7 GND GND G8 I/O I/O G9 I/O I/O ...

  • Page 124

    ... PLUS ProASIC Flash Family FPGAs 256-Pin FBGA 16 15 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner v5 ...

  • Page 125

    ... E2 I/O I/O E3 I/O I/O E4 I/O I/O E5 I/O I/O E6 v5.9 PLUS ProASIC Flash Family FPGAs 256-Pin FBGA APA150 APA300 APA450 APA600 Function Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 126

    ... I/O I/O I/O I/O I GND GND GND GND GND GND GND GND GND GND GND GND APA600 Function GND DDP I/O I/O I/O I/O I/O / GL1 NPECL1 AGND I GND GND GND GND V DD I/O NPECL2 AGND I/O / GL4 I/O / GL2 PPECL1 / ...

  • Page 127

    ... GND GND N14 V V DDP DDP N15 I/O I/O N16 v5.9 PLUS ProASIC Flash Family FPGAs 256-Pin FBGA APA150 APA300 APA450 APA600 Function Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 128

    ... I/O I/O I/O TDI TDI TDO TDO GND GND I/O I/O I/O I/O v5.9 256-Pin FBGA APA150 APA300 APA450 APA600 Function Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 129

    ... FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.9 PLUS ProASIC Flash Family FPGAs 3-45 ...

  • Page 130

    ... V V DDP DDP D1 I/O I/O D2 I/O I I/O D4 GND GND D5 I/O I/O D6 I/O I/O v5.9 484-Pin FBGA Pin APA450 APA600 Number Function Function D7 I/O I/O D8 I/O I/O D9 I/O I/O D10 I/O I/O D11 I/O I/O D12 I/O I/O D13 I/O I/O D14 ...

  • Page 131

    ... I/O I/O H20 H21 I/O I/O H22 I/O I/O J1 I/O I/O J2 I/O I I/O J4 I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 484-Pin FBGA Pin APA450 APA600 Number Function Function J5 I/O I/O J6 I/O I/O J7 I/O I DDP DDP J9 GND GND J10 J11 J12 ...

  • Page 132

    ... I/O I/O N17 I/O I/O N18 I/O I/O N19 I/O I/O N20 NC I/O N21 I/O I/O N22 I/O I/O v5.9 484-Pin FBGA Pin APA450 APA600 Number Function Function P1 I/O I/O P2 I/O I/O P3 I/O I/O P4 I/O I/O P5 I/O I/O P6 I/O I/O P7 I/O ...

  • Page 133

    ... I/O V16 I/O I/O V17 TDI TDI V18 V19 TDO TDO V20 GND GND v5.9 PLUS ProASIC Flash Family FPGAs 484-Pin FBGA Pin APA450 APA600 Number Function Function V21 NC I/O V22 I/O I I/O W2 I/O I/O W3 I/O I/O W4 GND GND W5 I/O I/O ...

  • Page 134

    ... AA22 GND GND AB1 GND GND AB2 GND GND AB3 V V DDP DDP AB4 I/O I 484-Pin FBGA Pin APA450 APA600 Number Function Function AB5 I/O I/O AB6 I/O I/O AB7 I/O I/O AB8 I/O I/O AB9 I/O I/O AB10 I/O I/O ...

  • Page 135

    ... FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx v5.9 PLUS ProASIC Flash Family FPGAs A1 Ball Pad Corner 3-51 ...

  • Page 136

    ... I/O I/O C14 I/O I/O C15 I/O I/O C16 I/O I/O C17 I/O I/O C18 I/O I/O v5.9 676-Pin FBGA Pin APA600 APA750 Number Function Function C19 I/O I/O C20 I/O I/O C21 I/O I/O C22 I/O I/O C23 I/O I/O ...

  • Page 137

    ... G16 I/O I/O G17 NC NC G18 I/O I/O G19 V V DDP DDP v5.9 PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function G20 NC NC G21 I/O I/O G22 I/O I/O G23 I/O I/O G24 I/O I/O G25 ...

  • Page 138

    ... GND L16 GND GND L17 GND GND L18 L19 V V DDP DDP L20 NC NC v5.9 676-Pin FBGA Pin APA600 APA750 Number Function Function L21 I/O I/O L22 I/O I/O L23 I/O I/O L24 I/O I/O L25 I/O I/O L26 I/O I/O ...

  • Page 139

    ... R16 GND GND R17 GND GND R18 R19 V V DDP DDP v5.9 PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function R20 NC NC R21 I/O I/O R22 I/O I/O R23 I/O I/O R24 I/O I/O R25 I/O ...

  • Page 140

    ... DDP W17 V V DDP DDP W18 V V DDP DDP W19 W20 V V DDP DDP v5.9 676-Pin FBGA Pin APA600 APA750 Number Function Function W21 I/O I/O W22 I/O I/O W23 I/O I/O W24 I/O I/O W25 I/O I/O W26 I/O I/O Y1 ...

  • Page 141

    ... I/O AC18 I/O I/O AC19 I/O I/O AC20 I/O I/O AC21 I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function AC22 TMS TMS AC23 RCK RCK AC24 I/O I/O AC25 I/O I/O AC26 I/O ...

  • Page 142

    ... AF8 I/O I/O AF9 I/O I/O AF10 I/O I/O AF11 I/O I/O AF12 I/O I/O AF13 I/O I 676-Pin FBGA Pin APA600 APA750 Number Function Function AF14 I/O I/O AF15 I/O I/O AF16 I/O I/O AF17 I/O I/O AF18 I/O I/O AF19 ...

  • Page 143

    ... FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.9 PLUS ProASIC Flash Family FPGAs 3-59 ...

  • Page 144

    PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function A2 GND GND A3 GND GND A4 I/O I/O A5 GND GND A6 I/O I/O A7 GND GND A8 I/O I/O A9 I/O I/O A10 I/O I/O ...

  • Page 145

    FBGA Pin APA750 APA1000 Number Function Function D15 I/O I/O D16 I/O I/O D17 I/O I/O D18 I/O I/O D19 I/O I/O D20 I/O I/O D21 I/O I/O D22 I/O I/O D23 I/O I/O D24 I/O I/O D25 I/O ...

  • Page 146

    PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function G27 I/O I/O G28 I/O I/O G29 I/O I/O G30 GND GND H1 I/O I/O H2 I/O I/O H3 I/O I/O H4 I/O I/O H5 I/O I/O ...

  • Page 147

    FBGA Pin APA750 APA1000 Number Function Function L9 NC I/O L10 NC I/O L11 L12 L13 L14 L15 L16 ...

  • Page 148

    PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function P21 V V DDP DDP P22 I/O I/O P23 I/O I/O P24 I/O I/O P25 I/O I/O P26 I/O I/O P27 I/O I/O P28 I/O I/O P29 ...

  • Page 149

    FBGA Pin APA750 APA1000 Number Function Function V3 I/O I/O V4 I/O I/O V5 I/O I/O V6 I/O I/O V7 I/O I/O V8 I/O I I/O V10 V V DDP DDP V11 V12 ...

  • Page 150

    PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function AA15 V V DDP DDP AA16 V V DDP DDP AA17 V V DDP DDP AA18 V V DDP DDP AA19 V V DDP DDP AA20 NC ...

  • Page 151

    FBGA Pin APA750 APA1000 Number Function Function AD27 I/O I/O AD28 I/O I/O AD29 I/O I/O AD30 GND GND AE1 I/O I/O AE2 AE3 I/O I/O AE4 I/O I/O AE5 I/O I/O AE6 GND GND ...

  • Page 152

    PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function AH9 I/O I/O AH10 I/O I/O AH11 I/O I/O AH12 I/O I/O AH13 I/O I/O AH14 I/O I/O AH15 I/O I/O AH16 I/O I/O AH17 I/O I/O ...

  • Page 153

    ... FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.9 PLUS ProASIC Flash Family FPGAs 3-69 ...

  • Page 154

    PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Number Function Number GND A4 GND A5 GND A6 I A10 V DD A11 I/O A12 GND A13 I/O ...

  • Page 155

    FBGA 1152-Pin FBGA Pin APA1000 Pin Number Function Number E15 I/O F18 E16 I/O F19 E17 I/O F20 E18 I/O F21 E19 I/O F22 E20 I/O F23 E21 I/O F24 E22 I/O F25 E23 I/O F26 E24 I/O F27 ...

  • Page 156

    PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Number Function Number J27 I/O J28 V DDP J29 I/O J30 I/O J31 I/O J32 GND J33 I/O J34 I/O K4 I/O K5 ...

  • Page 157

    FBGA 1152-Pin FBGA Pin APA1000 Pin Number Function Number I/O R10 P8 I/O R11 P9 I/O R12 P10 I/O R13 P11 I/O R14 P12 V R15 DDP P13 V R16 DD P14 ...

  • Page 158

    PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Number Function Number V16 GND V17 GND V18 GND V19 GND V20 GND V21 GND V22 V DD V23 V DDP V24 I/O V25 I/O V26 I/O V27 I/O V28 PPECL2 ...

  • Page 159

    FBGA 1152-Pin FBGA Pin APA1000 Pin Number Function Number AB27 I/O AC30 AB28 I/O AC31 AB29 I/O AC32 AB30 I/O AC33 AB31 I/O AC34 AB32 I/O AD1 AB33 I/O AD2 AB34 I/O AD3 AC1 GND AD4 AC2 GND AD5 ...

  • Page 160

    PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Number Function Number AG5 I/O AG6 I/O AG7 I/O AH10 AG8 GND AH11 AG9 I/O AH12 AG10 I/O AH13 AG11 I/O AH14 AG12 I/O AH15 AG13 I/O AH16 AG14 I/O AH17 ...

  • Page 161

    FBGA 1152-Pin FBGA Pin APA1000 Pin Number Function Number AL17 I/O AM20 AL18 I/O AM21 AL19 I/O AM22 AL20 I/O AM23 AL21 I/O AM24 AL22 I/O AM25 AL23 I/O AM26 AL24 I/O AM27 AL25 I/O AM28 AL26 I/O AM29 ...

  • Page 162

    ... PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA 101112131415 161718 19 20 2122 23 25 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx Top View D A1 Corner Index Area Bottom View v5 Side View ...

  • Page 163

    ... C17 I/O I/O C18 I/O I/O C19 GND GND C20 I/O I/O C21 I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function C22 I/O I/O C23 GND GND C24 C25 I/O I/O D1 I/O I/O ...

  • Page 164

    ... G20 I/O I/O G21 I/O I/O G22 I/O I/O G23 I/O I/O G24 I/O I/O G25 I/O I/O H1 I/O I/O v5.9 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function H2 I/O I/O H3 GND GND H4 I/O I/O H5 I/O I/O H6 I/O I/O H7 I/O I/O H8 ...

  • Page 165

    ... M1 I/O I/O M2 I/O I/O M3 I/O I/O M4 AGND AGND M5 NPECL1 NPECL1 M6 I/O / GL2 I/O / GL2 v5.9 PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function M7 I/O / GLMX1 I/O / GLMX1 DDP DDP M9 GND GND M10 M11 GND GND M12 ...

  • Page 166

    ... I/O I/O R24 I/O I/O R25 I/O I/O T1 I/O I/O T2 I/O I/O T3 I/O I/O T4 I/O I/O T5 I/O I/O T6 I/O I/O T7 I/O I DDP DDP T9 GND GND v5.9 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function T10 T11 T12 T13 T14 T15 T16 ...

  • Page 167

    ... I/O Y11 I/O I/O Y12 I/O I/O Y13 I/O I/O Y14 I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function Y15 I/O I/O Y16 I/O I/O Y17 GND GND Y18 I/O I/O Y19 TCK ...

  • Page 168

    ... I/O AD14 I/O I/O AD15 I/O I/O AD16 I/O I/O AD17 I/O I/O AD18 I/O I/O AD19 I/O I/O v5.9 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function AD20 I/O I/O AD21 I/O I/O AD22 I/O I/O AD23 AD24 GND GND ...

  • Page 169

    ... The "Temperature Grade Offerings" table grade in the following device/packages: APA300-FG144 APA300-FG256 APA600-FG256 APA600-FG484 APA600-FG676 APA1000-FG896 v5.2 90° and 270° phase shift support was removed from the datasheet. (December 2005) The "Ordering Information" section The last paragraph of the The Output Frequency Range in the The title for Table 2-19 • ...

  • Page 170

    PLUS ProASIC Flash Family FPGAs Previous version Changes in current version (v5.9) v5.1 MIL-STD-883 was added to the datasheet. V and V were changed CCI Table 2-9 • Temperature and Voltage Derating Factors v5.0 In the "208-Pin ...

  • Page 171

    ... Figure 2-45 • FIFO Reset. Table 2-68 • 0°C to 110° was updated in the "Pin Description" was updated for the APA600 and APA1000. Please review all was updated. was updated. was updated. PLUS and ProASIC Military/Aerospace datasheets were combined. This was updated. ...

  • Page 172

    PLUS ProASIC Flash Family FPGAs Previous version Changes in current version (v5.9) PLUS v3.2 The "ProASIC Figure 2-11 • PLL Block – Top-Level View and Detailed PLL Block Diagram Table 2-7 • Clock-Conditioning Circuitry MUX Settings Figure 2-17 • Using ...

  • Page 173

    Previous version Changes in current version (v5.9) v2.0 The following pins have been changed in the (continued) Pin Number "144-Pin TQFP" section The following pins have been changed in the Pin Number ...

  • Page 174

    PLUS ProASIC Flash Family FPGAs Previous version Changes in current version (v5.9) v2.0 The following pins have been changed in the (continued) Pin Number PLUS Advance v0.7 The "ProASIC The "Array Coordinates" section The "Power-Up ...

  • Page 175

    Previous version Changes in current version (v5.9) Advance v0.6 The "Calculating Typical Power Dissipation" section (continued) The "Absolute Maximum Ratings*" section The "Programming, Storage, and Operating Limits" section The "Nominal Supply Voltages’ section was updated. The "Recommended Operating Conditions" section ...

  • Page 176

    ... All pinout tables have been updated, and several packages are new: 208-Pin PQFP – APA150, APA300, APA450, APA600 456-Pin PBGA – APA150, APA300, APA450, APA600 144-Pin FBGA – APA150, APA300, APA450 256-Pin FBGA – APA150, APA300, APA450, APA600 676-Pin FBGA – APA600 Advance v0.1 Figure 2-20 • APA1000 Memory Block Architecture ...

  • Page 177

    ...

  • Page 178

    ... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. ...