APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 7

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

Figure 1-3 • Core Logic Tile
Live at Power-Up
The Actel flash-based ProASIC
Level 0 of the live at power-up (LAPU) classification
standard. This feature helps in system component
initialization,
processor wakes up, setting up and configuring memory
blocks, clock generation, and bus activity management.
The LAPU feature of flash-based ProASIC
greatly simplifies total system design and reduces total
system cost, often eliminating the need for complex
programmable logic device (CPLD) and clock generation
PLLs that are used for this purpose in a system. In
addition, glitches and brownouts in system power will
not corrupt the ProASIC
and unlike SRAM-based FPGAs, the device will not have
to be reloaded when system power is restored. This
enables the reduction or complete removal of the
configuration
brownout detection, and clock generator devices from
the PCB design. Flash-based ProASIC
total system design, and reduce cost and design risk,
while increasing system reliability and improving system
initialization time.
In 3 (Reset)
In 2 (CLK)
In 1
executing
PROM,
PLUS
expensive
critical
device's flash configuration,
PLUS
PLUS
tasks
voltage
devices support
devices simplify
before
PLUS
monitor,
devices
the
v5.9
Flash Switch
Unlike SRAM FPGAs, ProASIC
ISP flash switch as its programming element.
In the ProASIC
floating
information. One is the sensing transistor, which is only
used for writing and verification of the floating gate
voltage. The other is the switching transistor. It can be
used in the architecture to connect/separate routing nets
or to configure logic. It is also used to erase the floating
gate
Logic Tile
The logic tile cell
of which can be inverted) and one output (which can
connect to both ultra-fast local and efficient long-line
routing resources). Any three-input, one-output logic
function (except a three-input XOR) can be configured as
one tile. The tile can be configured as a latch with clear
or set or as a flip-flop with clear or set. Thus, the tiles can
flexibly map logic and sequential gates of a design.
(Figure 1-2 on page
gate,
PLUS
(Figure
flash switch, two transistors share the
which
1-2).
1-3) has three inputs (any or all
ProASIC
Local Routing
Efficient Long-Line Routing
stores
PLUS
PLUS
uses a live-at-power-up
the
Flash Family FPGAs
programming
1-3