APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 64

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

Embedded Memory Specifications
This section discusses ProASIC
memory and its interface signals, including timing
diagrams that show the relationships of signals as they
pertain to single embedded memory blocks
Table 2-13 on page 2-21
configurations. Simultaneous read and write to the same
location must be done with care. On such accesses the DI
bus is output to the DO bus. Refer to the
RAM and FIFO Blocks
information.
Enclosed Timing Diagrams—SRAM Mode:
Table 2-51 • Memory Block SRAM Interface Signals
2 -5 4
SRAM Signal
WCLKS
RCLKS
RADDR[0:7]
RBLKB
RDB
WADDR[0:7]
WBLKB
DI[0:8]
WRB
DO[0:8]
RPE
WPE
PARODD
Note: Not all signals shown are used in all modes.
ProASIC
•
•
•
•
"Synchronous SRAM Read, Access Timed Output
Strobe (Synchronous Transparent)" section on
page 2-55
"Synchronous SRAM Read, Pipeline Mode Outputs
(Synchronous Pipelined)" section on page 2-56
"Asynchronous SRAM Write" section on page 2-57
"Asynchronous SRAM Read, Address Controlled,
RDB=0" section on page 2-58
PLUS
Flash Family FPGAs
Bits
1
1
8
1
1
8
1
9
1
9
1
1
1
shows basic SRAM and FIFO
application note for more
PLUS
SRAM/FIFO embedded
In/Out
Out
Out
Out
In
In
In
In
In
In
In
In
In
In
(Table
ProASIC
Write clock used on synchronization on write side
Read clock used on synchronization on read side
Read address
True read block select (active Low)
True read pulse (active Low)
Write address
Write block select (active Low)
Input data bits [0:8], [8] can be used for parity In
Output data bits [0:8], [8] can be used for parity Out
Read parity error (active High)
Write parity error (active High)
Selects odd parity generation/detect when high, even when low
Negative true write pulse
2-51).
PLUS
v5.9
The difference between synchronous transparent and
pipeline modes is the timing of all the output signals
from the memory. In transparent mode, the outputs will
change within the same clock cycle to reflect the data
requested by the currently valid access to the memory. If
clock cycles are short (high clock speed), the data
requires most of the clock cycle to change to valid values
(stable signals). Processing of this data in the same clock
cycle is nearly impossible. Most designers add registers at
all outputs of the memory to push the data processing
into the next clock cycle. An entire clock cycle can then
be used to process the data. To simplify use of this
memory
implemented as part of the memory primitive and are
available to the user in the synchronous pipeline mode.
In this mode, the output signals will change shortly after
the second rising edge, following the initiation of the
read access.
•
•
• Embedded Memory Specifications
"Asynchronous SRAM Read, RDB Controlled"
section on page 2-58
"Synchronous SRAM Write"
setup,
Description
suitable
registers
have
been