APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 84

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

V
This pin may be connected to any voltage between GND
and 16.5 V during normal operation, or it can be left
unconnected.
programming,
ProASIC
floating the pin or connecting it to V
V
This pin may be connected to any voltage between 0.5 V
and –13.8 V during normal operation, or it can be left
unconnected.
programming,
ProASIC
floating the pin or connecting it to GND.
Recommended Design Practice
for V
ProASIC
APA750, APA1000
Bypass capacitors are required from V
to GND for all ProASIC
During the erase cycle, ProASIC
current surges on the V
only way to maintain the integrity of the power
distribution to the ProASIC
current surges is to counteract the inductance of the
Figure 2-46 • ProASIC
2. There is a nominal 40 kΩ pull-up resistor on V
3. There is a nominal 40 kΩ pull-down resistor on V
2 -7 4
PP
PN
ProASIC
PLUS
PLUS
PN
PLUS
PLUS
/V
Devices
Devices
2
3
Flash Family FPGAs
For information on using this pin during
For information on using this pin during
PP
Devices – APA450, APA600,
see
see
Programming Supply Pin
Programming Supply Pin
PLUS
application note. Actel recommends
application note. Actel recommends
PLUS
the
the
PP
V
PP
and V
devices during programming.
and V
PLUS
In-System
In-System
ProASIC
PLUS
PN
Device
Actel
PN
device during these
DDP
power supplies. The
Capacitor Requirements
PP
PLUS
devices may have
.
to GND and V
PP
V
V
Programming
Programming
PP
PN
.
PN
0.01 µF
0.01 µF
.
0.1 µF
0.1 µF
to
to
2.5cm
PN
4.7 µF
4.7 µ F
v5.9
finite length conductors that distribute the power to the
device. This can be accomplished by providing sufficient
bypass capacitance between the V
GND (using the shortest paths possible). Without
sufficient
inductance, the V
spike beyond the voltage that the device can withstand.
This issue applies to all programming configurations.
The solution prevents spikes from damaging the
ProASIC
the V
capacitor with a 25 V or greater rating. To filter low-
frequency noise (decoupling), use a 4.7 µF (low ESR, <1
<Ω, tantalum, 25 V or greater rating) capacitor. The
capacitors should be located as close to the device pins as
possible (within 2.5 cm is desirable). The smaller, high-
frequency capacitor should be placed closer to the device
pins than the larger low-frequency capacitor. The same
dual-capacitor circuit should be used on both the V
V
ProASIC
APA300
These devices do not require bypass capacitors on the V
and V
the programming cable and the trace length on the
board is less than or equal to 30 inches. Note: For trace
lengths greater than 30 inches, use the bypass capacitor
recommendations in the previous section.
PN
+
+
pins
PP
PN
PLUS
and V
(Figure
pins as long as the total combined distance of
PLUS
bypass
devices. Bypass capacitors are required for
PN
2-46).
Programming
Devices – APA075, APA150,
pads. Use a 0.01 µF to 0.1 µF ceramic
PP
Supplies
Header
capacitance
or
and V
+
_
_
+
PN
pins may incur a voltage
to
PP
and V
counteract
PN
pins and
PP
and
the
PP