APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 169

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version
v5.8
(June 2009)
v5.7
(September 2008)
v5.6
(August 2008)
v5.5
(February 2007)
v5.4
(October 2006)
v5.3
(May 2006)
v5.2
(December 2005)
The –F speed grade is no longer supported and was removed from the datasheet.
A note regarding RoHS compliant packages was added to the
The
Input, VCO (Voltage Controlled Oscillator), and Output frequencies, and the acquisition time.
Table 2-10 • PLL I/O Constraints
Table 2-23 • DC Electrical Specifications (V
Applies to Commercial and Industrial Temperature Only
now only applies to commercial and industrial temperature ranges.
Specifications (V
and MIL-STD-883B Temperature Only
military temperature. The V
have been made to the drive currents at which 3.3 V V
and are now split by slew rate. In addition in
changed from 0.8 V to 0.7 V for 3.3 V Schmitt-trigger input operation.
V
2.5 V ±0.2 V) Applies to Military Temperature and MIL-STD-883B Temperature Only
changed back to the data in v5.5.
V
V and V
Only.
A statement about single cell and cascaded cell timing diagrams was added to the
Timing Diagrams – FIFO Mode:"
The following pins were updated in the
Pin Number Updated Function
C2
F1
The heading, MIL-STD-883B, and note 4 were added to the
The
grade in the following device/packages:
APA300-FG144
APA300-FG256
APA600-FG256
APA600-FG484
APA600-FG676
APA1000-FG896
90° and 270° phase shift support was removed from the datasheet.
The
The last paragraph of the
The Output Frequency Range in the
The title for
updated.
The caption was updated in
Changes in current version (v5.9)
OH
OH
"PLL Electrical Specifications" table
"Temperature Grade Offerings" table
"Ordering Information" section
and V
and V
DD
OL
OL
= 2.5 V ±0.2 V) Applies to Military Temperature and MIL-STD-883B Temperature
data was updated in
data in
Table 2-19 • Military Temperature Grade Product Performance Retention
I/O / GL1
I/O / GL2
DDP
= 3.3 V ±0.3 V and V
Table 2-24 • DC Electrical Specifications (V
"Boundary Scan (JTAG)" section
OH
Figure 2-45 • FIFO
and V
section.
is new.
Table 2-24 • DC Electrical Specifications (V
"Timing Control and Characteristics"
was updated to include RoHS information.
OL
is based on
specifications were updated in
"144-FBGA Pin"
was updated significantly. Changes were made to the
was updated to include the military (M) temperature
DD
v5.9
DDP
= 2.5 V ±0.2 V) Applies to Military Temperature
Table
Reset.
= 3.3 V ±0.3 V and V
Table 2-23
2-24, the maximum V
OH
is the same table that was in v5.7, but it
table:
and V
was updated.
"Device Resources"
"Device Resources"
but
OL
DDP
voltage levels are measured
Table 2-24
Table 2-24 • DC Electrical
= 3.3 V ±0.3 V and V
Table
section.
DD
IL
2-24, and changes
= 2.5 V ±0.2 V)
DDP
specification has
ProASIC
only applies to
table.
= 3.3 V ±0.3
table.
"Enclosed
PLUS
DD
was
was
Flash Family FPGAs
=
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