APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 16

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

Input/Output Blocks
To meet complex system demands, the ProASIC
family offers devices with a large number of user I/O
pins; up to 712 on the APA1000.
available supply voltage configurations (the PLL block
uses an independent 2.5 V supply on the AVDD and
AGND pins). All I/Os include ESD protection circuits. Each
I/O has been tested to 2000 V to the human body model
(per JESD22 (HBM)).
Six or seven standard I/O pads are grouped with a GND
pad and either a V
pad. Two reference bias signals circle the chip. One
protects the cascaded output drivers, while the other
creates a virtual V
I/O pads are fully configurable to provide the maximum
flexibility and speed. Each pad can be configured as an
input, an output, a tristate driver, or a bidirectional
buffer
Table 2-4 •
2 -6
Function
I/O pads configured as inputs
I/O pads configured as outputs
I/O pads configured as bidirectional
buffers
ProASIC
(Figure 2-6
PLUS
I/O Features
Flash Family FPGAs
DD
and
DD
supply for the I/O ring.
Table
(core power) or V
2-4).
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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Table 2-3
Selectable 2.5 V or 3.3 V threshold levels
Optional pull-up resistor
Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can be
configured as an input only, not a bidirectional buffer. This input type may be slower than
a standard input under certain conditions and has a typical hysteresis of 0.35 V. I/O macros
with an "S" in the standard I/O library have added Schmitt capabilities.
3.3 V PCI Compliant (except Schmitt trigger inputs)
Selectable 2.5 V or 3.3 V compliant output signals
2.5 V – JEDEC JESD 8-5
3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)
3.3 V PCI compliant
Ability to drive LVTTL and LVCMOS levels
Selectable drive strengths
Selectable slew rates
Tristate
Selectable 2.5 V or 3.3 V compliant output signals
2.5 V – JEDEC JESD 8-5
3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)
3.3 V PCI compliant
Optional pull-up resistor
Selectable drive strengths
Selectable slew rates
Tristate
DDP
(I/O power)
shows the
PLUS
v5.9
Table 2-3 •
Figure 2-6 • I/O Block Schematic Representation
Input Compatibility
Output Drive
Description
ProASIC
3.3 V / 2.5 V Signal Control Drive
Strength and Slew-Rate Control
EN
A
Signal Control
Y
3.3 V / 2.5 V
PLUS
I/O Power Supply Voltages
Control
Pull-up
2.5 V
2.5 V
2.5 V
Pad
V
DDP
3.3 V
3.3 V
3.3 V