APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 6

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

ProASIC
The
granularity comparable to gate arrays.
The ProASIC
(Figure
logic function (e.g., NAND gate, D-Flip-Flop, etc.) by
programming
interconnections
Tiles and larger functions are connected with any of the
four levels of routing hierarchy. Flash switches are
distributed
nonvolatile, reconfigurable interconnect programming.
Flash switches are programmed to connect signal lines to
Figure 1-1 • The ProASIC
Figure 1-2 • Flash Switch
1 -2
ProASIC
proprietary
1-1). Each tile can be configured as a three-input
PLUS
PLUS
PLUS
throughout
Flash Family FPGAs
(Figure 1-2
device core consists of a Sea-of-Tiles
the
ProASIC
Architecture
PLUS
appropriate
PLUS
Device Architecture
and
the
Figure 1-3 on page
Word
architecture
device
flash
to
Sensing
provides
provide
switch
1-3).
v5.9
Floating Gate
the appropriate logic cell inputs and outputs. Dedicated
high-performance lines are connected as needed for fast,
low-skew global signal distribution throughout the core.
Maximum core utilization is possible for virtually any
design.
ProASIC
SRAM blocks with built-in FIFO/RAM control logic.
Programming
asynchronous operation, two-port RAM configurations,
user-defined depth and width, and parity generation or
checking.
Specifications"
information.
PLUS
Refer
devices also contain embedded, two-port
Switching
Switch In
Switch Out
options
section
to
RAM Block
256x9 Two-Port SRAM
or FIFO Block
I/Os
Logic Tile
RAM Block
256x9 Two Port SRAM
or FIFO Block
the
on
include
page 2-54
"Embedded
synchronous
for
Memory
more
or