APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 40

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles.
This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as
follows:
P
P
P
P
=> P
P
=> P
P
=> P
P
=> 361 mW
P
P
2 -3 0
=> P
=> P
=> P
clock
storage
logic
outputs
inputs
memory
dc
ac
total
ProASIC
+ P
ms
mc
C
V
Fp
N
Fs
R
q
Fq
p
outputs
inputs
memory
load
DDP
memory
clock
storage
logic
ac
= 374 mW (typical)
= 10 MHz
= 13,440
PLUS
= 0 (no logic tiles in this shift register)
= 0 mW
= (P1 + (P2*R) - (P7*R
= 13,440 (in a shift register 100% of storage tiles are toggling at each clock cycle and Fs = 10 MHz)
= P8 * q * Fq = 0.3 mW
=
=
=
=
= (P4 + (C
= P5 * ms * Fs = 147.8 mW
= 0 mW
=
=
Flash Family FPGAs
40 pF
3.3 V
24
5 MHz
=
1
10 MHz
0 (no RAM/FIFO blocks in this shift register)
load
* V
DDP
2
2
)) * Fs = 121.5 mW
)) * p * Fp = 91.4 mW
v5.9